enriiexposed/das-fdi

Asignatura optativa de la FDI - UCM sobre el diseño de circuitos de tamaño medio usando herramientas de descripcion de hardware automáticas (VHDL, Verilog sobre Vivado)

Language: VHDL - Size: 165 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 1 - Forks: 0

AkinduID/Nano-Processor-Final

This Repository contains source files for a 4-bit nanoprocessor designed in VHDL using Xilinx Vivado

Language: VHDL - Size: 887 KB - Last synced at: 3 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 1

phucthaiv02/FPGA-project

Language: Verilog - Size: 22.5 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

bizkiwi/verilog-fpga-pingpong-game

Design and implementation of an electronic game using Verilog and the Basys3 Field Programmable Gate Array (FPGA) kit.

Language: Verilog - Size: 3.96 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Prajjv/RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

Language: Tcl - Size: 146 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 4 - Forks: 1

sthanikan2000/Simple-Nano-Processor 📦

Simple Nano Processor | Group Project for CS1050-Computer Organization & Digital Design | Semester 02

Size: 12.9 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

NonRoute/HW_SYN_LAB_I_Project 📦

2110363 Hardware Synthesis Lab I (2022/1) - Term Project

Language: C - Size: 28.5 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

chclau/basys3_Magellan

Magellan - A HW monitor/debugger for Basys 3

Language: VHDL - Size: 375 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0