GitHub / aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
Stars: 2
Forks: 0
Open issues: 0
License: None
Language: TeX
Size: 191 KB
Dependencies parsed at:
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Created at: over 1 year ago
Updated at: over 1 year ago
Pushed at: over 1 year ago
Last synced at: 2 months ago
Topics: artix, artix-7, axi, axi-lite, axi-memory-mapped, axi-stream, basys3, embedded, fpga, hls, vitis, vitis-hls, vivado, vivado-ip-integrator, vivado-vitis, xilinx, xilinx-fpga, xilinx-hls, xilinx-vitis, xilinx-vivado
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