vhdl-code | Topic | Ecosyste.ms: Repos

Topic: "vhdl-code"

Alexandra07e/AC-secret

Arhitectura Calculatoarelor (VERILOG) - probleme rezolvate de mine (edaplayground flood)

Size: 1.95 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

MohammedS2lah/Digital_Design_With_VHDL

In this repository, I'll provide a simple, organized collection of VHDL designs and tutorials to help anyone learn and practice digital design using VHDL.

Language: VHDL - Size: 36.1 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

mohammadamintahmasbi/AMA-Cach-RAM

Final project of VHDL lession, AMA Cach-RAM

Language: C - Size: 3.92 MB - Last synced at: 7 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

dita-deb/VHDL_Labs

All labs from CPE 3020 compiled into one single repository -Anindita

Language: VHDL - Size: 79.1 KB - Last synced at: 6 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

CodeNKoffee/clock-simulation

VHDL simulation of a digital clock for the CSEN605 course at the German University in Cairo. Includes clock generation and stimulus processes.

Language: VHDL - Size: 1000 Bytes - Last synced at: 5 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

SaBuMa/Juego-Pong-en-VHDL--VHDL-Pong-Game

Juego Pong en VHDL // VHDL Pong-Game

Language: VHDL - Size: 32.9 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

SaBuMa/Procesador-en-VHDL-VHDL-Processor

VHDL Processor

Language: VHDL - Size: 2 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

MuriloBarros304/lab-circuitos-digitais

Aplicações de Circuitos Digitais em VHDL

Language: VHDL - Size: 43.6 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

rgeleon/VHDL_samples

Vhdl coursework

Language: VHDL - Size: 620 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.

Language: VHDL - Size: 58.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

rafidmuhammad/vhd-adder4

4-bit adder with outputs consists of sum and carry out

Language: VHDL - Size: 1.95 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ITSUREN/ComputerArchitecture

🏛️ [RUSHED🏃‍♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.

Language: VHDL - Size: 707 KB - Last synced at: 8 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Sadegh-Khedry/VHDL-Projects

This repository contains various VHDL projects showcasing digital logic circuits implemented using VHDL.

Language: C - Size: 1.25 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

Language: Verilog - Size: 383 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Elem404/Designing-and-Testing-Asynchronous-FIFO-Queues

Design and simulation for Asynchronous FIFO Queues in VHDL (with bacher's odd-even sort)

Language: VHDL - Size: 1.65 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

melanie-t27/Logic-Design-Project

Project for the Reti Logiche Course at @POLIMI, instructed by Prof. Gianluca Palermo during the academic year 2022/23

Language: VHDL - Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpDownCounter

A 4-bit up-down counter is a digital circuit capable of counting both upwards and downwards in binary, typically controlled by an up/down input signal.

Language: VHDL - Size: 41 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4Bit_UpCounter

A 4-bit up counter is a digital circuit that increments its output by one with each clock pulse, counting from 0000 to 1111 in binary, and resetting back to 0000 after reaching 1111.

Language: VHDL - Size: 39.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-2x4Decoder

The VHDL code implements a 2x4 decoder, converting two input signals into four output signals based on the input combinations.

Language: VHDL - Size: 40 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-4x1MUX

The VHDL code implements a 4x1 multiplexer (MUX), selecting one of four input signals based on the two select lines and producing a single output.

Language: VHDL - Size: 42 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

CodiieSB/VHDL-DFlipFlop

The VHDL code describes a D flip-flop with synchronous reset functionality.

Language: VHDL - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

MaksymAndreiev/CompEngineering

Workshop on the course "Methods and Technologies of Computer Engineering" at V. N. Karazin Kharkiv National University

Language: VHDL - Size: 9.77 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mariateodorapopescu/vhdl_fsm

A team-project about a fem vending-machine I had in 2nd year of uni

Language: VHDL - Size: 10.7 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Man2Dev/Hardware-Software-Codesign-course

Some of my Hardware Software Codesign projects

Language: C - Size: 2.4 MB - Last synced at: 9 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

GraceSevillano/RTIC-project-Antoine-s-army

This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed

Language: VHDL - Size: 12.3 MB - Last synced at: 9 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

DavidRosero/FPGAWorldCodes

Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL

Language: VHDL - Size: 382 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 2

Man2Dev/Computer-Architecture-course

Some of my Computer Architecture projects

Language: C - Size: 9.68 MB - Last synced at: 9 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Ad-Vi/dino-led

Dino-chrome project on a 7*5 LED Matrix in VHDL

Language: VHDL - Size: 11.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

mostafapiran/VHDL-for-FPGA

My projects in VHDL language for FPGA in Modelsim software

Language: VHDL - Size: 11.4 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

SamsonAdem/HW_SW_Co_Design_FPGA

Hardware accelerator for Image processing in FPGA

Language: C++ - Size: 41.7 MB - Last synced at: almost 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

DericAugusto/ISN2023_DigitalSystems

Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.

Language: VHDL - Size: 40.8 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

josefdc/Laboratorio-Fundamentos-De-Electronica

Este repositorio es el hogar del curso de Fundamentos de Electrónica de la Universidad Tecnológica de Pereira. Aquí, los estudiantes y profesores pueden colaborar en el desarrollo y mejora continua del curso, compartiendo materiales didácticos, ejercicios prácticos, proyectos y más.

Language: VHDL - Size: 222 KB - Last synced at: 27 days ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 2

qzxtu/Basys3MusicNotes

A VHDL code that produces 8 musical notes (do, re, mi, fa, sol, la, si and do-8va) in Basys 3, one for each switch.

Language: Tcl - Size: 10.7 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ArimondoScrivano/Progetto_Reti_Logiche 📦

progetto di Reti Logiche 2022/2023 del Politecnico di Milano

Language: VHDL - Size: 483 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

lorenzozaccomer/iterative-multiplier

Project for Electronic Calculators course.

Language: VHDL - Size: 4.77 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Prottasha19/adder-design

IC design with 8-bit adder.

Language: VHDL - Size: 11.7 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

medamine101/VHDL_Bowling

Bowling Game in VHDL, the ._files are due to working on this project in both Windows and Linux systems

Language: VHDL - Size: 86.2 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Bryce-Leung/FPGA-UART-Protocol

UART Protocol made for Altera DE2-115 FPGA in VHDL

Language: VHDL - Size: 46.9 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 1

lovc21/VHDL-code-from-lab

This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.

Language: VHDL - Size: 73.2 KB - Last synced at: 8 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

chclau/basys3_Magellan

Magellan - A HW monitor/debugger for Basys 3

Language: VHDL - Size: 375 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

touunix/Keyboard-reading-PS-2-VHDL

Keyboard reading PS/2 VHDL | Odczyt klawiatury PS/2 VHDL

Language: VHDL - Size: 14.6 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

rajsinghtech/MIPS-Single-Cycle-Processor

CPRE 381 Project 1 - Single Cycle Processor

Language: HTML - Size: 130 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

ZiliottoFilippoDev/FIR-Filter-VHDL-Implementation Fork of micheleavella/fir_filter_VHDL

FPGA implementation via VHDL and Python simultation for a low-pass FIR Filter. Testbenches before the implmentation are also available.

Language: Jupyter Notebook - Size: 1.52 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

nickdpz/Procesador-para-resolver-sistemas-matriciales

Este proyecto consta de un procesador dedicado para resolver sistemas matriciales de 3x3.Se ingresan los datos por medio de tecla con comunicacion serial ya que esta el diseño de los driver. La visualizarcion de los resultados con dos decimales de exactitud, Se visualiza los resultados finales en los leds de una FPGA, con posibilidades de visualizacion en una LCD.

Language: VHDL - Size: 650 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0