KayeJD/NexysA7-FPGA-Programming

Embedded Programming Projects

Language: Tcl - Size: 56.6 KB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

fm16191/fpga-vector-add

vector-add scripts using oneAPI and targeting FPGA devices. Verifications made on Intel's devcloud.

Language: C++ - Size: 44.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

kocatepedogu/cellular-automaton-processor

A simple processor with a grid of cores that can only interact with their immediate neighbors

Language: SystemVerilog - Size: 211 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Mesbah-Lab-UCB/DNN_MPC_Plasma_FPGA

Project files for a neural network (NN) implementation on an FPGA using Vivado HLS.

Language: Verilog - Size: 3.01 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

narajoEmmanuel/Millisecond-Counter-Circuit

Language: Verilog - Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

KatelynLam97/-Digital-Systems-Project-Microwave

Size: 84 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

GraceSevillano/RTIC-project-Antoine-s-army

This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed

Language: VHDL - Size: 12.3 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Robin329/VerilogThings

Some exercises on verilog.

Language: Verilog - Size: 76.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

AtlasFPGA/MULTICORE-ESdUDO-ROJO

Diseñar la placa - ¡Créalo tu mismo! De coste más reducido para la Fpga CYC1000, con una BLUEPILL STM32F103C8T6

Size: 22.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

jjgar11/Digital-2

Desarrollo para la materia de Electronica Digital 2

Language: Verilog - Size: 15.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

matthewyjiang/fpga-blind-maze

EE354 (Intro to Digital Circuit Design) - Final Project by Matthew Jiang and Kelvin Cao

Language: Verilog - Size: 70.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

peplxx/keyboard-driver-vhdl

Driver for handling matrix keyboard 4x4 on FPGA Board

Language: Verilog - Size: 2.93 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

tiagosr/gategen

Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like

Language: Racket - Size: 16.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ngrabbs/arm_projects

ARM single cycle processor on nandland.com go-board

Language: SystemVerilog - Size: 20.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

10x-Engineers/Infinite-ISP_Firmware

Infinite-ISP Image Signal Processing Pipeline Firmware for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit (coming soon).

Size: 9.77 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

playduck/xvcd-jlink Fork of fantomgs/xvcd-jlink

XVC 1.0 daemon j-link support for Vivado

Language: C - Size: 11.2 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 1

DericAugusto/ISN2023_DigitalSystems

Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.

Language: VHDL - Size: 40.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

mlab-modules/PROGLOG01

Small low-power open-source toolchain compatible FPGA

Language: HTML - Size: 46.5 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

skrevolve/FPGA

FPGA learning course

Size: 4.88 KB - Last synced at: about 1 month ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

z4chh/FPGA_Slot_Machine

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.

Language: SystemVerilog - Size: 12.7 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

ArnaudPoletto/epfl-cs208-tetris-project

Experience the classic arcade game in a whole new way! Play Tetris in Assembly and master the art of arranging falling blocks. Challenge your reflexes and strategic thinking in this nostalgic journey. Ready to achieve new high scores? Let the Tetris frenzy begin! 🎮🧱

Language: Assembly - Size: 8.79 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

yilmaz0734/FPGATictactoegame

In this project, we implemented a different kind of a tic tac toe board game that is played on an FPGA board using its push buttons. We used Verilog HDL to code the project and implemented a VGA interface for visualization.

Language: Verilog - Size: 22.8 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Thibesan/FPGA-AttendanceChecker

C program that interacts with FPGA Board to validate Attendence requests based on established paramaters

Language: C - Size: 5.86 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Petrus97/8bit-Microprocessor

8 bit microprocessor design on FPGA for Digital Electronic Design with VHDL in Uppsala University.

Language: VHDL - Size: 972 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Edw590/Pong-in-FPGA-on-RISC-V-CPU Fork of IObundle/iob-soc-pong

Pong game with NES controller clones for the Digilent FPGA Dev Board Basys 3, coded in Verilog and C with IOb-SoC as base

Language: C - Size: 183 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

lmlimasd/Automatic-meal-dispenser-for-pets

Design a meal dispenser for pets controlled by a user via WIFI through a smartphone app. Project course - integration techniques.

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NourMamdouh/RSA_project

RSA project (in verilog), originally done to run on Xilinx SPARATAN-6 board (FPGA)

Language: Verilog - Size: 10.7 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

gyxxc/tinyMIPS

an uncompleted tiny MIPS32 soft core based on Altera Cyclone-IV EP4CE10F17C8

Language: Verilog - Size: 98.6 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

zhang-stephen/hdlbits-sv-solutions

SystemVerilog Solutions to exercise from HDLBits

Language: SystemVerilog - Size: 11.7 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

wesamnabeel99/FPGA_LAB

This repository is intended for students who study Electrical Engineering at University of Baghdad, as well as anyone else who wants to learn about FPGA programming.

Language: VHDL - Size: 1.37 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

0marAmr/Single_Cycle_RISC-V_processor

Language: Verilog - Size: 563 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

algorhtym/booths_multiplier

Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method

Language: VHDL - Size: 6.84 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

MarianaGranados-09/VGA-videogame

VGA videogame with FPGA

Language: VHDL - Size: 183 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

sanjeewasamarasinghe/nanobit-Logic-Analyzer

This repository belongs to FPGA based Logic Analyzer.

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avikram2/PacmanFPGA

ECE 385 Final Project on DE-10 FPGA Board with NIOS 2 SoC: Implementing PacMan

Language: Verilog - Size: 482 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

charkster/xc3sprog-cmod_a7-rpi

Xc3sprog compiled for Raspberry Pi with support for Numonyx (Micron) N25Q 0x16 memory which is on the Cmod-A7 FPGA board.

Language: Shell - Size: 650 KB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

EliaFantini/ContrastEQ-VHDL-module-of-a-contrast-equalizer-for-FPGAs

VHDL module of a contrast equalizer to be implemented on FPGAs

Language: VHDL - Size: 638 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

EnesErcin/Image_Preprocessing_wFPGA

FPGA design that can apply basic filters to the image data using block ram.

Language: Verilog - Size: 43.5 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

Abhinand20/Secure-AES

Verilog code for my paper that proposes a secure-AES algorithm with support for various FPGA boards.

Language: Verilog - Size: 101 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1

PauloMaced0/Washing_machine

Washing machine simulation using an FPGA

Language: VHDL - Size: 3.25 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

henrikhestnes/CSE237C-Validation-and-Testing-of-Embedded-Systems

Repository for the course CSE237C - Validation and Testing of Embedded Systems at University of California San Diego.

Language: Jupyter Notebook - Size: 143 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

CodeWithAbbas/FPGA-Designing

It contains the VHDL coding of basic combinational and sequential circuits as well as top level design including Datapath and Controller

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AnDa-creator/TLC_ee705Verilog

Language: Verilog - Size: 2.92 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

WilliamSilveiraF/mastermind

:joystick: Mastermind game written in VHDL

Language: VHDL - Size: 386 KB - Last synced at: 4 days ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

skni-kod/6502_FPGA

Our implementation of 6502 CPU in Verilog

Language: Verilog - Size: 207 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

madmaverickminion/Soil-monitoring-bot

This repository contains all the work(till task 5) of Soil Monitoring Bot theme(eYRC-2021-22).

Language: Verilog - Size: 26.7 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

alperklnc/two-player-minesweeper

Simulation of the classic mine sweeper game on a SPARTAN 3A FPGA board. *Term Project for Koç University ELEC 204: Digital Design course

Language: VHDL - Size: 475 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

talhatallat/Electronics

Size: 19.3 MB - Last synced at: 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 1

Dirakon/FPGA-Controlling-PC

FPGA project: board connects to PC via cable, the user sends instructions (e.g. mouse move, mouse set, write a number, write a letter, etc) via FPGA interface.

Language: Verilog - Size: 111 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Project-Nios2-DMA-Accelerator

Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.

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SakaSerbia/FPGA-DE10-Standard-Simple-Nios2-Project

Designing a simple processor system on FPGA. This is demo project to test FPGA DE10-Standard and develop a simpe Nios2 app.

Language: Verilog - Size: 1.37 MB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Blinking-LED

First FPGA Project done on FPGA DE10-Standard. Simple blinking of LED.

Language: Verilog - Size: 32.2 KB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

wolfdroid/Integer_Calculator

Simple RTL model for Interger Numbers Calculation using RAM and 7 Segment Display.

Language: VHDL - Size: 1.79 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

Liberxue/awesome-FPGA

FPGA

Size: 3.91 KB - Last synced at: 12 days ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

uyarahmet/2D-intersection-calculator

2D Intersection Calculator in VHDL programming language.

Language: VHDL - Size: 242 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

hajin-kim/FPGA_AXI_and_VHDL

FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain

Language: VHDL - Size: 2.41 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

mohammad-safari/Smart_House

Final_Project_Logic_Circuits_Design_Fall_1399

Language: Verilog - Size: 12.2 MB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

davidcawork/ElectronicDesign-uah

UAH Telecommunication Engineering Master's Electronic Design Subject

Language: VHDL - Size: 10.2 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

paulohepimentel/mips

Implementation of a simplified version of the MIPS data path

Language: Verilog - Size: 294 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

einstein07/HC08-datapath

Implements a datapath which is capable of executing a subset of the Motorola HC08 instruction set on a Field Programmable Gate Array (FPGA).

Language: C - Size: 249 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

sankalpgambhir/petris

An FPGA based Tetris clone, with an emulated VGA output running on SDL.

Language: Verilog - Size: 761 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

kutayeroglu/two-player-minesweeper 📦

Simulation of the classic mine sweeper game on a SPARTAN 3A FPGA board. *Term Project for Digital Design course

Language: VHDL - Size: 404 KB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

einstein07/Vivado-IP-and-Resource-Usage

Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

Language: VHDL - Size: 12.8 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

JakubKajzer/AudioSteganography

A concept of audio steganography accelerated with FPGA.

Language: VHDL - Size: 69.4 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

MasterERTS/embel-calculator

Calculator on FPGA

Language: VHDL - Size: 5.5 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

urmilmodi/ECE241

Programs created in Verilog for the ECE241 (Digital Systems) course

Language: Verilog - Size: 46.5 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

zjjxwhh/FPGA

FPGA Demo | NEUQ 生产实习 FPGA 例程

Language: Verilog - Size: 51.9 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

micro-FPGA/MEGA65-Hacks

Hacks and non standard things with MEGA65 Computer

Size: 39.1 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

eta-sys/coe-File-converter-for-FPGA-programming

Converts any file to coe format.

Size: 618 KB - Last synced at: 7 months ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 0