MEESAM749/Single-Cycle-Non-Pipelined-MIPS-32-Processor

This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

Language: C - Size: 1.97 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

pboechat/ice40up5k_tests

Multiple test designs for the iCE40UP5K-B-EVN board.

Language: Verilog - Size: 35.3 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 1 - Forks: 0

Kj0ric/fpga-battleship-game

A digital implementation of the classic Battleship game on the Sipeed Tang Nano 9K FPGA. Features a 4x4 grid with LED and seven-segment displays, two-player support, and best-of-three rounds gameplay.

Language: Verilog - Size: 2.53 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 1

GAbeGH/Keypad

FPGA-Based Digital Lock System with Digital Noise Filter

Language: C - Size: 7.83 MB - Last synced at: 17 days ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

Awrsha/FPGA-Programming

Advanced FPGA implementations of cutting-edge deep learning models, optimized for high performance and energy efficiency.

Language: VHDL - Size: 113 KB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

UCL-Proton-Beam-Therapy/VHDL_vivado_basic

A guide on how to write basic FPGA programming in VHDL and its implementation. This targeted the one who has no experience with Vivado.

Language: Tcl - Size: 104 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

Aom92/FPGA-Effects-Pedal

Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite

Language: Jupyter Notebook - Size: 210 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 0

socks2309/neural-network-fpga

This project is part of the B.Tech degree in Electronics and Telecommunication Engineering at KIIT University.

Language: Verilog - Size: 21.5 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 1 - Forks: 1

ATalhaTimur/Micro_CSE4117

special microprocessor design

Language: C - Size: 158 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

codr-void/portfolio.io

Wa'el Engineering Project Repository

Language: Python - Size: 80.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

Shuregg/FPGA-practicum

learning about FPGA

Language: SystemVerilog - Size: 1.24 MB - Last synced at: 2 months ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

JN513/estudos_verilog

Exemplos feito em verilog para estudos

Language: Verilog - Size: 10.6 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Ineso1/VerilogModules

A collection of educational and practical Verilog modules for FPGA design, tested on Delite FPGA MAX 10 with Intel Quartus and ModelSim. Includes utilities like Clock Dividers, Debouncers, Decoders, State Machines, and more.

Language: Verilog - Size: 254 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Raveem13/HDLbits-practice-solution

This is a repository containing my solutions to the problem statements given on HDLBits website.

Language: Verilog - Size: 150 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

marco-milanesi/FlybackConverter-FPGA-based-Digital-Twin

Repository containing code, libraries, schematics, and 3D models from the paper 'FPGA-Based Digital Twin Implementation for Power Converter System Monitoring.

Language: Verilog - Size: 211 MB - Last synced at: 10 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

Bradford-Miller/fpga-support

Common-Lisp library to support FPGA-based processor development

Language: Common Lisp - Size: 404 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

peplxx/Morse-Coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

Language: HTML - Size: 10 MB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

alibukharai/embedded_system

This repository is primarily designed for my personal learning, featuring small projects and demonstration code based on ESP-32 and STM-32 platforms. Its main focus revolves around Real-Time Operating Systems (RTOS) and CPU architecture exploration.

Language: C - Size: 163 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

NatsuDrag9/ethernet-switch

Design of 4-port gigabit ethernet switch

Language: VHDL - Size: 4.34 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

incoder-mru/StocNoC-Accelerating-Stochastic-Models-Through-Reconfigurable-Network-on-Chip-Architectures Fork of dsdnu/sisNoC

Reconfigurable network on chip architecture for accelerating stochastic models

Language: VHDL - Size: 14.2 MB - Last synced at: 16 days ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

gaikwadabhishek/flappy-bird-fpga-vhdl

Flappy Bird on FPGA using VHDL

Language: HTML - Size: 119 KB - Last synced at: 5 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

nedaraad/MSc-Synthesis

Homework and Project for Master Course (Synthesis of Digital Systems)

Language: VHDL - Size: 1.14 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

AhmedERady/Grad_Project

Smart Automation Controller for Precision Agriculture

Language: V - Size: 124 MB - Last synced at: 4 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

EmperorPenguin18/assembler

Mini SRC assembler for school project

Language: C - Size: 18.6 KB - Last synced at: 5 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

bizkiwi/verilog-fpga-pingpong-game

Design and implementation of an electronic game using Verilog and the Basys3 Field Programmable Gate Array (FPGA) kit.

Language: Verilog - Size: 3.96 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

ali-asnaashari/CORDIC-Algorithm

Implementation of the CORDIC machine in circular rotation mode

Language: C++ - Size: 2.09 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

davimoreno/quadrature_oscillator

Low Cost FPGA Quadrature Oscillator

Language: Verilog - Size: 225 KB - Last synced at: 6 months ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

Gunmetal-61/Adafruit_SSD1306_MicroBlaze Fork of jmwilson/Adafruit_SSD1306_MicroBlaze

A fork which adds I2C support to a Xilinx Microblaze port/fork of an Arduino SSD1306 OLED display library.

Language: C++ - Size: 156 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

b-garbacz/Neokeon128

Implementation of the neokeon block cipher

Language: Verilog - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

Sarthak-Singh/Counter-on-7segment-VLSI

A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

Language: C - Size: 1.09 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

gustavomotadev/engg57-ransac

Application of the RANSAC algorithm in embedded C and Verilog for Altera Nios II and Cyclone IV E.

Language: Verilog - Size: 36.7 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

sethi-bhumika/FPGA-Design

FPGA design for implementing encoder, adder and counter circuits. (using logic tiles and switch boxes)

Language: Verilog - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

ilyajob05/verilog_SPI

SPI module for Nexys 4 Artix-7 FPGA Trainer Board

Language: Verilog - Size: 38.1 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Marslanali/fpga_vertex_6_gtx_Interface 📦

Vertex 6 FPGA GTx Transciever Simulation in Xilinx ISE using Xilinx IP Core

Language: Verilog - Size: 10.4 MB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

ckevar/IIR-Filter

IIR Filter for audio application

Language: VHDL - Size: 10.7 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 4

styczen/Reconfigurable-Systems

Verilog sources for FPGA Zybo board implementing vision algorithms.

Language: VHDL - Size: 230 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

HuangDave/MIPS

Single-Cycle and 5-stage Pipelined SoC

Language: Verilog - Size: 44.3 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

Holandsoest/FPGA_I2C

WIP: An I2C-master AXI-slave, and I2C-Slave. So I can practice myself a bit, and build my own libraries.

Language: VHDL - Size: 299 KB - Last synced at: 3 days ago - Pushed at: 3 days ago - Stars: 0 - Forks: 0

ab-ff/Multi-Bit-Comparator

Variations of a multi-bit generalized comparator for different area and timing.

Size: 1000 Bytes - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

tom-zv/FPGA-ESP32-Projects

Projects showcase

Language: VHDL - Size: 261 KB - Last synced at: 4 days ago - Pushed at: 4 days ago - Stars: 0 - Forks: 0

roi-ri/Laboratorio-Sistemas-Digitales-I

Repo para almacenar los laboratorios desarrollados durante el curso de Sistemas Digitales I - IE0323 impartido en la carrera de Ingeniería Eléctrica en la Universidad de Costa Rica (UCR)

Language: Tcl - Size: 17.6 MB - Last synced at: 11 days ago - Pushed at: 11 days ago - Stars: 0 - Forks: 0

manzoorambekar/learning-vhdl

A collection of VHDL projects and exercises for learning digital design, covering basic to intermediate concepts with simulations in ModelSim and synthesis for FPGAs.

Language: VHDL - Size: 9.77 KB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0

TahirZia-1/FPGA-Morse-Code-Encoder

Converts digits (only) into its Morse code on a NEXYS 4 DDR Board, displayed using LED lights. 1 second for dot and 3 seconds for Dash. Can be toggled into different modes for storing digits in FIFO register as well.

Language: HTML - Size: 6.36 MB - Last synced at: 21 days ago - Pushed at: 21 days ago - Stars: 0 - Forks: 0

Awais-Asghar/FPGA-Based-Smart-Car-Security-System

A Smart Anti-Theft Car Security System implemented on FPGA to detect and prevent unauthorized access. The system uses real-time monitoring and control logic to enhance vehicle safety and response.

Language: Verilog - Size: 17.5 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

megiemee/chopsticksFPGA

Arcade game implemented in lucid based on the "Chopsticks" game done on Alchitry Labs for 50.002 Computational Structures..

Size: 31.3 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

DebbieMatt/FPGA_VHDL

Objetivo do Projeto Implementação de circuitos digitais em FPGA. Exemplos de lógica combinacional, sequencial e sistemas embarcados. Testes práticos com periféricos (LEDs, botões, displays, etc.).

Language: VHDL - Size: 21.8 MB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

ThuyPham/FPGA-Toturial

FPGA Tutorial Basic thuypx.com

Language: VHDL - Size: 16.6 KB - Last synced at: about 1 month ago - Pushed at: about 1 month ago - Stars: 0 - Forks: 0

rastin-py/NeonBlaster-an-Arcade-Shooting-Game-on-FPGA

An arcade game implemented in VHDL as an assignment for Digital Systems Analysis & Design course at the University of Guilan, Department of Computer Engineering, presented in Fall 2023 by Dr. Mahdi Aminian.

Language: VHDL - Size: 55.3 MB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

SKpro-glitch/Multi-Bit-Comparator

Variations of a multi-bit generalized magnitude comparator for different area and timing.

Language: D - Size: 275 KB - Last synced at: 23 days ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

OTANK10/FIR-Filter-FPGA-Implementation

Implementing a 4-tap FIR filter on the Intel DE1-SoC FPGA using Verilog HDL

Language: Verilog - Size: 17.6 KB - Last synced at: about 2 months ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

ElecGeek/PulsesGene

Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.

Language: VHDL - Size: 184 KB - Last synced at: about 1 month ago - Pushed at: about 2 months ago - Stars: 0 - Forks: 0

Gaby130905/7-segmentos-letras

verilog

Language: SystemVerilog - Size: 8.79 KB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

HANANDA1/FPGA-Based-Smart-Car-Security-System

FPGA-Based Smart Car Security System is a robust solution for protecting high-end vehicles like Porsche. It uses Verilog and SystemVerilog to detect unauthorized access and disable the fuel pump, ensuring your car remains secure. 🛠️🚗

Language: Verilog - Size: 9.27 MB - Last synced at: 2 months ago - Pushed at: 2 months ago - Stars: 0 - Forks: 0

nesterovmaxim31/Simpson-s-rule-Verilog

Построение синхронного цифрового автомата для реализации метода Симсона с дальнейшей загрузкой на ПЛИС Artix-7 xс7a100tcsg324-1I

Language: Verilog - Size: 1.36 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

Sanugiw/FPGA

UA UART communication module using Verilog on a DE0-Nano FPGA with real-time serial data transfer, and verified functionality with a custom test bench.

Size: 3.49 MB - Last synced at: 1 day ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

dannyvanderpol/nexys_a7_projects

Projects for the Nexys A7 FPGA development board

Language: Tcl - Size: 4.01 MB - Last synced at: 3 months ago - Pushed at: 3 months ago - Stars: 0 - Forks: 0

AnamikaS2005/Audio-based-authentication-system-for-access-control-using-Boolean-FPGA

This project implements a secure, touchless access control system using voice-based authentication on a Boolean FPGA (Spartan-6). It combines Python-generated audio and Verilog-based FPGA design to analyze and compare dominant audio frequencies, allowing access only when the voice patterns match.

Size: 1.68 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

HarmandeepArneja/ReflexRush

Reaction Time Testing Game

Language: Verilog - Size: 0 Bytes - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

MistGhost/FPGA-AudioProcessingSystem

2024第八届全国大学生集成电路创新创业大赛获奖作品，基于紫光同创FPGA的音频处理系统。由本人负责的软件部分项目代码工程。

Language: Python - Size: 7.62 MB - Last synced at: 4 months ago - Pushed at: 4 months ago - Stars: 0 - Forks: 0

AzuratiX/Realtime-Radar-Using-FPGA-Basys3

This was our final group project. We started with little knowledge about servo control, ultrasonic sensors, or VGA display—but through this project, we learned a lot and were thrilled to see everything work smoothly in the end.

Language: Verilog - Size: 0 Bytes - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

HMarchiori/relogio-xadrez-vhdl

Este projeto implementa um relógio de xadrez utilizando a linguagem VHDL. O sistema gerencia o tempo de jogo de dois jogadores e exibe os tempos restantes em um display.

Language: Tcl - Size: 8.79 KB - Last synced at: 18 days ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

TahirZia-1/RISC-V-CPU-Core-SystemVerilog

This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.

Language: SystemVerilog - Size: 11.9 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

TahirZia-1/UART

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: about 1 month ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 166 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

specpose/software-on-silicon

Object oriented, templated building blocks that should be able to run on an fpga. A standard interface for integrating system on chip (SOC).

Language: C++ - Size: 627 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

ahp-electronics/fpga-template

Lattice FPGA Verilog project template

Language: TeX - Size: 115 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

CFZRfrndVolt/Introducing-VHDL-

This repository contains projects and experiments focused on designing, simulating, and implementing digital circuits using VHDL (VHSIC Hardware Description Language) and Quartus II software. The projects covered in this repository serve as an introduction to key concepts in digital system design, including the creation of basic logic circuits, com

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gundasrikar/FPGA-Verilog-Code-Samples

Language: Verilog - Size: 29.3 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

jakunzler/asic_fpga_introduction

Web page for the ASIC and FPGA Repository

Language: Dockerfile - Size: 63.9 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

ishifr/fpga_prototyping_codes

FPGA prototyping by Verilog examples kitobini o'qish davomida yozilgan kodlar to'plami. Nexys4DDR(Artix-7) dev board'dan foydalanilgan. A collection of code written while reading the book FPGA prototyping by Verilog examples. Nexys4DDR(Artix-7) dev board is used

Language: Tcl - Size: 0 Bytes - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Emibuglioni/Digital_Voltmeter

Language: Jupyter Notebook - Size: 68.4 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

Reallyummy/FPGA_Drawing_WeakNote

This project is a drawing program for Basys3 FPGA board. This code is written for Verilog. Enjoy!!! :)

Language: Verilog - Size: 12.7 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

OP-Patel/Gomoku

Gomoku on a DE1-SoC Board

Language: Verilog - Size: 662 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

YogeshGoyyalA-1/FPGA_PROJECT

This project implements real-time image processing on an Artix-7 FPGA using VGA display. It applies filters like negative, grayscale, and color thresholding to images stored in Block RAM. The filters are controlled via hardware switches, and the processed image is displayed on a VGA monitor.

Language: Tcl - Size: 60.5 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

h0nt3d/modulo2345UpDownCounter

A counter written in VHDL that has been designed to count in radix 8 up and down from 0 to 2344 in radix 14 while displaying the counting on 4 Seven Segment Displays

Language: VHDL - Size: 8.79 MB - Last synced at: 6 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

alisayurev/fpga-vga-mem-game

A rhythm-based memory game implemented on an FPGA. The game displays a sequence of MIDI notes on a screen, which players must mimic to score points. This project combines hardware and game development to create an interactive experience that tests memory and timing, using an FPGA to generate and process MIDI signals in real-time.

Language: VHDL - Size: 2.93 KB - Last synced at: 6 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Keerthi2134/FPGA-code

Simple Digital Signal Processing Accelerator

Language: Verilog - Size: 2.93 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

agolajko/fpga-tinkering

Language: Verilog - Size: 122 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

DatNguyen97-VN/NN_RGB_FLAPPY_BIRD

:bird: A game of flappy bird for one player, plays by controlling the bird using a hand tracking mechanism

Language: SystemVerilog - Size: 159 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

gcardi/HDL

Informational materials for a course on logic networks, HDLs and programmable logic arrays (FPGAs).

Size: 34.4 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

thomaslaner/academicProjects

A portfolio of technical projects completed during my studies at the Technical University of Vienna, covering areas like digital design, data analytics, embedded systems, and enterprise architecture.

Language: Jupyter Notebook - Size: 38.3 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

MassimoGiacobbe/da_converter

pwm and ppm da converters on fpga, connected to a custom nyos II processor generated via the qsys tool on quartus prime, the processor is then programmed to use the DACs both with the serial interface and with some predefined inputs.

Language: C - Size: 49.9 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

chesskiss/SysVerilog_game_DonkeyKong

Here you'll find the game "Donkey Kong" written 100% in SysVerilog. You'll need an FPGA card, a screen, a keyboard, and audio devices for the full functionality.

Language: SystemVerilog - Size: 40.9 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

errray/fpga-spaceship

This space ship game project, where the spaceship is positioned at the center and objects coming from different directions can be hit using FPGA buttons, has been implemented with Verilog coding in quartus environment for Altera System-on-Chip (SoC) FPGA and VGA for display.

Language: Verilog - Size: 656 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

SaBuMa/Juego-Pong-en-VHDL--VHDL-Pong-Game

Juego Pong en VHDL // VHDL Pong-Game

Language: VHDL - Size: 32.9 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

mongshil553/Digital-Engineering-Verilog-Assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

Language: Verilog - Size: 4.88 KB - Last synced at: 6 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Swarup1747/Cache-Compression-Implementation-on-FPGA-using-Verilog-HDL

Cache Compression using Verilog HDL

Size: 82 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

kk26nav/Verilog-Experiments

Collection of all verilog experiments

Language: Verilog - Size: 562 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

arjunxvaish/Connect-Four

connect four game, Verilog

Language: SystemVerilog - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Prithvish04/channel_encoding_veterbi_decoding

Language: HTML - Size: 1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ARMCoderBR/BenEatersSAP1

A FPGA implementation of Ben Eater's SAP-1 computer using the Digilent's BASYS 3 board.

Language: Verilog - Size: 852 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

cztee/Lattice_iCEStick_SelfStudy_Notes

Language: VHDL - Size: 4.44 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

shahed22/Dadda-8-bit

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Language: Verilog - Size: 11.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

wjh776a68/sv_pcie

Simple implementation of PCIE4C-based pcie transfer on Xilinx Ultrascale+ FPGAs

Language: Tcl - Size: 122 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

jash0803/Simple_Elevator_Design

During the EL-203 course, we had to make a elevator controller project under Professor Biswajit Mishra.

Language: Verilog - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aslak3/spi-flasher

Pi Pico based SPI flash flasher

Language: C - Size: 15.6 KB - Last synced at: 8 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

krish1925/Logic-Design-Verilog

Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

Language: Tcl - Size: 8.53 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cp024s/100-days-of-RTL

probable journey of RTL coding ft. Chandra Prakash

Language: Verilog - Size: 292 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Davide-Ettori/Memory_Interaction-Hardware-Component-FPGA

Digital Circuits Design Project (PoliMi, year 2022) - Memory Interaction

Language: VHDL - Size: 7.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

zahi1/Digital-Electronics

Digital Electronics repo includes Boolean algebra and logic circuit design, covering topics such as gates, combinational and sequential circuits. It will help you learn logical circuit design principles, analyze circuits using automated tools, and delve into VHDL coding for the design and implementation of digital circuits on FPGA devices.

Size: 2.42 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0