GitHub topics: processor-architecture

Repositories

laudominik/6502_emulator

Language: Python - Size: 73.2 KB - Last synced at: 6 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

ILoveBacteria/CA-project-mips Fork of ngnma/CA-project-mips

My Computer Architecture project

Language: SystemVerilog - Size: 22.5 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ciriatico/OAC-Labs-UnB Fork of gustavodezan/oac-labs

Laboratórios da disciplina de Organização e Arquitetura de Computadores, ofertada na Universidade de Brasília (UnB) no semestre de 2021.2.

Language: Assembly - Size: 6.11 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

levindoneto/MIPS

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

Size: 1.17 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 5 - Forks: 0

digital-design-snu/RNBIP_SingleBusProcessor

Single Bus Processor - Summer Project 2016

Language: Verilog - Size: 26.4 KB - Last synced at: about 1 year ago - Pushed at: about 7 years ago - Stars: 8 - Forks: 0

AymenSekhri/Softcore-CPU

Implementation of a soft-core CPU and an assembler

Language: VHDL - Size: 2.09 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

nefelimet/mips-verilog

A simple MIPS processor in Verilog.

Language: Verilog - Size: 239 KB - Last synced at: 8 days ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

sarthakmittal92/risc-proc

Repository for the course project done as part of CS-230 (Digital Logic Design & Computer Architecture) course at IIT Bombay in Spring 2022.

Language: VHDL - Size: 5.37 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Alireza-Zwolf/MIPS-PROCESSOR

An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.

Language: SystemVerilog - Size: 1.76 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

suyashmahar/urisc

Single instruction processor and toolchain

Language: SystemVerilog - Size: 90.8 KB - Last synced at: 2 days ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

expjel/CSE-141L-Project Fork of ecstaticstupidity/CSE-141L-Project

Processor design project featuring 9-bit ISA 🤖

Size: 17.1 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

ciriatico/lcl_zeptoprocessador-iii

Projeto final de Laboratório de Circuitos Lógicos (LCL), disciplina ofertada na Universidade de Brasília (UnB) no semestre 2021.1.

Size: 1.31 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

maxislash/Tomasulo

Python simulator of Tomasulo algorithm

Language: Python - Size: 47.9 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1

AbhijayS/RISC-Processor-Logisim

16-bit RISC Processor - 9 Instructions - Logisim

Size: 21.5 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

levindoneto/Neander

Hipotetic Processor Neander in VHDL.

Language: VHDL - Size: 81.1 KB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 1

lorainemg/s-mipsv2-processor

The project consists of designing a processor in LogiSim that implements the S-MIPSv2 (Simplified-MIPS Version 2) instruction set architecture.

Language: Python - Size: 250 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

mxligr/Custom-CPU

A VHDL design of a simple custom processor, designed as a project for the Structure of Computer Systems class // 3rd year, 1st semester @ TUCN

Language: VHDL - Size: 1.62 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

emptyloominaty/CpuSimJS

Language: JavaScript - Size: 88.9 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Shubhayu-Das/tomasulo-O3-with-prefetch

Continuation of a functional Tomasulo out-of-order processor, with a cache prefetcher and replacement policy. Implements most of the RV32I ISA.

Language: Python - Size: 563 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

iancraz/EV21-Processor Fork of electronica-5/TP2

EV21 RISC Processor Design

Language: Verilog - Size: 12 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

sskender/FerRISC

RISC ARM7 Assembly

Language: OpenEdge ABL - Size: 1.13 MB - Last synced at: 3 months ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

furkankayar/DEUARC

DEUARC RISC computer design in Quartus II 13.0

Language: VHDL - Size: 7.5 MB - Last synced at: 4 months ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

jsburke/bsv-cores

RISC-V cores based on Bluespec's Piccolo and Flute

Language: Python - Size: 133 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 1

arianhaddadi/MIPS-PIPELINE

A MIPS Processor Implementation Using Verilog HDL With Pipelining Feature.

Language: Verilog - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

Subangkar/Computer-Architecture-CSE-306-BUET

Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET

Language: VHDL - Size: 200 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 1

vaaceves/32bits-MIPS-processor-with-VHDL

32bits MIPS processor with VHDL project

Language: VHDL - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

permutationlock/superscalar_processor

Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.

Language: Python - Size: 168 KB - Last synced at: 4 months ago - Pushed at: almost 10 years ago - Stars: 1 - Forks: 1

MoemenGaafar/Single-Cycle-Processor

Structural implementation of a single cycle processor using Verilog. The processor handles the following set of instructions: lw, sw, Rtype instructions (add, sub, and, or, slt), addi, sll, lh.

Language: Verilog - Size: 912 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

albmoriconi/dispensa-mic

Dispensa didattica sul processore Mic-1

Language: TeX - Size: 1.66 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Javier-varez/mos6502_docs

MOS 6502 Processor Book

Size: 1.05 MB - Last synced at: 6 days ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

maxislash/8CPU

8-bit CPU in Verilog

Language: Verilog - Size: 317 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 2

layman-n-ish/Tests-on-Simple-Scalar

Contains source code to carry out tests & analyse the results of various branch predictors against each other. Additionally, demonstrates the benefits of cache-oblivious algorithms. Done as part of VL-803 Processor Architecture course at IIIT-B (Spring 2020).

Language: Shell - Size: 55.7 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0