GitHub topics: vhdl-code | Ecosyste.ms: Repos

mariateodorapopescu/vhdl_fsm

A team-project about a fem vending-machine I had in 2nd year of uni

Language: VHDL - Size: 10.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ad-Vi/dino-led

Dino-chrome project on a 7*5 LED Matrix in VHDL

Language: VHDL - Size: 11.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

This is the code for the multiple implementations of a finite state machine thermostat. There is an implementation in C for the dsPIC33EP64MC502, an implementation with VHDL, and an implementation with LabVIEW and DAQmx. TwithFPO_DAQmx.vi requires a MyDAQ to run the program.

Language: C - Size: 82 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Kazhuu/audio-synthesizer

Copy of old FPGA audio synthesizer project for DE2 development board

Language: VHDL - Size: 4.76 MB - Last synced at: 26 days ago - Pushed at: over 6 years ago - Stars: 8 - Forks: 0

mostafapiran/VHDL-for-FPGA

My projects in VHDL language for FPGA in Modelsim software

Language: VHDL - Size: 11.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

pratikbhuran/Up_Counter

VHDL implementation of Up counter.

Language: VHDL - Size: 13.7 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

santifs/simon-game-vhdl

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

Language: VHDL - Size: 7.94 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

santifs/ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Language: VHDL - Size: 6.83 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2

Subhankar2000/Xilinx-ISE-8.2i-EC792-VLSI-LAB

saving lab experiments in this repo, specific to MAKAUT ECE-2021 7th SEM(old syllabus)

Language: VHDL - Size: 13.8 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

shahjui2000/Push-Button-Door-VHDL-

Simulation of a push button door lock with a variable password

Size: 160 KB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

SamsonAdem/HW_SW_Co_Design_FPGA

Hardware accelerator for Image processing in FPGA

Language: C++ - Size: 41.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aliansgp/VHDL_Multipliers

Different Multipliers code in VHDL and Comparison

Language: C - Size: 1.35 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

aliansgp/VHDL_Adders

Different adders code in VHDL and Comparison

Language: C - Size: 1.3 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

mrtkp9993/VHDLExamples

VHDL examples.

Language: VHDL - Size: 39.1 KB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 8 - Forks: 0

aniekanBane/poly-eval-vhdl

Modelling and simulation of a polynomial evaluator in VHDL using stepwise refinement.

Language: VHDL - Size: 32.2 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

josefdc/Laboratorio-Fundamentos-De-Electronica

Este repositorio es el hogar del curso de Fundamentos de Electrónica de la Universidad Tecnológica de Pereira. Aquí, los estudiantes y profesores pueden colaborar en el desarrollo y mejora continua del curso, compartiendo materiales didácticos, ejercicios prácticos, proyectos y más.

Language: VHDL - Size: 222 KB - Last synced at: about 2 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 2

Stavros/LedToggle

An example for NIOS II processor to toggle a Led with a Button

Language: Verilog - Size: 13.2 MB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 1

Stavros/4bitCounterParLoad

A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder

Language: VHDL - Size: 3.11 MB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

DericAugusto/ISN2023_DigitalSystems

Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.

Language: VHDL - Size: 40.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

abdalla1912mohamed/-AES-encryption-and-decryption-platform-in-FPGA-communication

implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts

Language: C - Size: 1.14 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

hk-117/VHDL

Some example of vhdl code, using ghdl and gtkwave.

Language: VHDL - Size: 30.3 KB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

mtzor/PipelineProcessor

This is a basic pipeline processor implemented in VHDL

Language: VHDL - Size: 607 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

farbodfld/CoDesign-Course

Projects of CoDesign course at SBU

Language: VHDL - Size: 3.86 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

qzxtu/Basys3MusicNotes

A VHDL code that produces 8 musical notes (do, re, mi, fa, sol, la, si and do-8va) in Basys 3, one for each switch.

Language: Tcl - Size: 10.7 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

tristan-oa/ALU-in-VHDL

Building an ALU using VHDL

Size: 5.21 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

berkaybarlas/VHDL-Clock-Project

⏰ A Fully Functional Clock with alarm and snooze .

Language: VHDL - Size: 7.81 KB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 2

Megapiro/Progetto-RETI-2019

Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - a.a. 2018-2019

Language: VHDL - Size: 323 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 3

DavidRosero/FPGAWorldCodes

Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL

Language: VHDL - Size: 382 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 2

Steve-Teal/pumpkin-cpu

A small general purpose, scalable, 16-bit, 16 instruction CPU core written in VHDL

Language: C - Size: 83 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0

lovc21/VHDL-code-from-lab

This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.

Language: VHDL - Size: 73.2 KB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

lorenzozaccomer/iterative-multiplier

Project for Electronic Calculators course.

Language: VHDL - Size: 4.77 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

elbekka/Programacion-De-Hardware-VHDL

4 bits ALU with 2 entries of selection using structural vhdl

Language: VHDL - Size: 4.88 KB - Last synced at: over 1 year ago - Pushed at: almost 7 years ago - Stars: 7 - Forks: 1

BertVerrycken/BERT

Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)

Language: VHDL - Size: 52.7 KB - Last synced at: 6 months ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1

Bryce-Leung/FPGA-UART-Protocol

UART Protocol made for Altera DE2-115 FPGA in VHDL

Language: VHDL - Size: 46.9 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 1

AliceO2Group/alice-fit-fpga

ALICE Fast Interaction Trigger (FIT) FPGA code

Language: VHDL - Size: 32.2 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 4

IgnacioChirinos/MIPS-VHDL-Vivado

MIPS processor that performs matrix multiplication 3x3 based on VHDL and implemented in XILINX

Language: VHDL - Size: 296 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

HuzaifaElahi/Space-Invaders

Language: VHDL - Size: 7.81 KB - Last synced at: about 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

LucaLombardini/fft_sylvester_ii

Development and Testing of an Hardware achitecture dedicate to the FFT calculus based on Cooley-Tuckey's Algorithm

Language: VHDL - Size: 9.57 MB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Suvraneel/VHDL-Xilinx

Projects were generated in Xilinx v14.7 If you're using Xilinx you may simply import the projects. Otherwise just read the codes in .vhd extensioned files. ☮️

Language: C - Size: 9.47 MB - Last synced at: 7 days ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

datacipy/VHDL

Příklady ke knize Data, čipy, procesory

Language: VHDL - Size: 29 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 16 - Forks: 3

Tanmaymundra/vhdl

This repository contains example of logic such as comparator, encoder, etc in vhdl. Feel Free to add other examples in this repository

Language: VHDL - Size: 76.2 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

Sanchit-20/Ten_Bit_Multiplier

Designed 10 bit multiplier, implemented using structural and RTL level design, and the functionality of 10 bit adder is completely synchronous.

Language: VHDL - Size: 777 KB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

mustafa1728/Digital-Image-Filtering-VHDL

A VHDL description of a digital image filtering system on FPGAs. Part of COL215 course project.

Language: VHDL - Size: 3.3 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

tertiarycourses/FPGATraining

Exercise files for VHDL Programming Training for FPGA

Language: VHDL - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 0

JCLArriaga5/8-bit-counter_VHDL

Arquitectura en VHDL de un contador de 8 bits

Language: VHDL - Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

soumyadip007/VHDL-Modelsim-Altera-Simulator-COA

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

Size: 78.1 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1

Daymorelah/vendingMachine

A simple VHDL code that describes the hardware needed to implement a vending machine

Language: VHDL - Size: 485 KB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

idataaki/vhdl-projects

all projects of vhdl course of university

Language: VHDL - Size: 883 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

FranciscoMotta/VHDL-ADDER

Sumador implementado en VHDL.

Language: VHDL - Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 0

HembramBeta777/Digital-Logic-assignment-

VHDL___programming

Size: 38.1 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0

AlicePagano/MAPD-A-Project-IPBUS-Filter

FIR filter co-processor implementation in FPGA

Language: VHDL - Size: 40.1 MB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

lucaleoni7/project-retilogiche

Final Project - Reti Logiche. Politecnico di Milano, A.A. 2019-2020

Language: VHDL - Size: 782 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

obih9/Progetto-Reti-Logiche-2021

Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - a.a. 2020-2021

Language: VHDL - Size: 1.63 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

ZahraAbtahi/8_Bit_VHDL_Project

Language: VHDL - Size: 386 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

DantasB/hangman-game-vhdl

A simple Hangman game made using VHDL

Language: VHDL - Size: 611 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

Azzedine-prog/STOP-WATCH-AND-RTC-FPGA-FULL-PROJECT

STOP WATCH AND RTC FPGA FULL PROJECT

Language: VHDL - Size: 17.6 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

swapnilbembde/aes_128

VHDL Implementation of AES-128

Language: VHDL - Size: 43 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 2 - Forks: 5

VXAPPS/cmake-ghdl-compiler

GHDL Compiler Definition for CMake

Language: CMake - Size: 32.2 KB - Last synced at: 11 months ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

pat0s/vut-inc-project

Príjem a zasielanie dát na asynchrónnej sériovej linke

Language: VHDL - Size: 277 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

haideraheem/Programming-FPGA-Basys3-with-VHDL

This repository contains beginner to intermediate level of codes for VHDL and Basys 3.

Size: 6.53 MB - Last synced at: 6 months ago - Pushed at: almost 5 years ago - Stars: 2 - Forks: 1

DantasB/ula-vhdl

A simple ULA made using VHDL

Language: VHDL - Size: 1.92 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 1

BojanFaletic/fpga_ip

Collection of IP used in projects

Language: VHDL - Size: 9.68 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

talisma-cassoma/finite-state-machine-FSM

Moore and Mealy Machine architecture (model)

Language: VHDL - Size: 31.3 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

metehancaliskan/Not-Hitting-The-Obstacles

This project is my digital electronics project and is based on VHDL.

Size: 938 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

gitbritt/Computer_Architecture

Language: VHDL - Size: 294 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

Confizolo/PoDProjects

Various projects for Physics of Data master degree

Language: Jupyter Notebook - Size: 348 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

MostafaGalal1/Full-Adder-Subtractor

4-bit ripple adder, which adds 2 4-bit inputs introducing sum and carry signals and implementing. 1. Half adder. 2. Full adder using the half adder. 3. 4-bit ripple adder/subtractor using the full adder.

Language: VHDL - Size: 16.6 KB - Last synced at: 3 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

jhenals/VHDL-Code---Circuito-Sequenziale

Secondo Progetto di Elettronico Digitale AA2022-2023

Size: 4.33 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Bsingstad/FYS4220_2019_lab2

UiO, FYS4220, Lab 2, 2019

Language: VHDL - Size: 1.51 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

charrat0649/BE_VHDL_M2SME_Binome3

L’objectif de ce bureau d’étude est de concevoir le pilote de barre franche sous forme d’un système sur puce programmable SOPC (System On Programmable Chip) décrite à l’aide du langage de description de Hardware VHDL (Very High Speed Hardware Description Langage) en se basant sur l’analyse de spécifications et découpage fonctionnel du système choisi et la conception de circuits d’interfaces numériques en VHDL pour le simuler et le valider sur la maquette, puis faire des interfaçages avec les bus microprocesseur tels que NIOS, Altera, Avalon pour la validation du SOPC en manipulation.

Language: C - Size: 13.4 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

yishnu96/Number-Of-Once

VHDL PROGRAM

Language: HTML - Size: 109 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

Bsingstad/FYS4220_2019_lab1

UiO, FYS4220, Lab 1, 2019

Language: VHDL - Size: 5.94 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Liza23/Summer-of-Science_Automata-Theory

This repository contains the code written for implementation of digital circuits and is for the reading project on Automata theory under Summer of Science, conducted by Math & Physics Club, IIT Bombay.

Language: TeX - Size: 1.61 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 0

jhenals/VHDL-Code---Carry-Select-32bit

Progetto di Elettronica Digitale AA 2022-2023

Size: 4.67 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

asl0007/DSD-VHDL-

PROGRAMS OF VHDL

Language: VHDL - Size: 2.26 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

LukeKan/fpga-manhattan-distance

FPGA design project for the course "Reti Logiche" of Politecnico di Milano, a.y. 2018/2019

Language: VHDL - Size: 293 KB - Last synced at: almost 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

kevinkirsten/ControleSalaDeReunioesVHDL

Circuito de controle de sala de reuniões implementado em VHDL

Language: VHDL - Size: 4.37 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

rajsinghtech/MIPS-Pipelined-Processor

CPRE 381 Project 2 Pipelined Processor - Both hardware and software

Language: HTML - Size: 123 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

nicobidone/Arquitectura_de_computadoras_I-FCExa-UNICEN

Trabajo práctico especial. Materia: Arquitectura de computadoras I. Año: 2017. UNICEN.

Language: VHDL - Size: 3.57 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

LFMP/CDII

Language: VHDL - Size: 58.9 MB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 1

DoCodeForever/vhdl

Size: 535 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Bruno-Messias/EEL5105-Circuitos-e-Tecnicas-Digitais 📦

Material sobre projetos das aulas de CTD

Language: VHDL - Size: 3.1 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

MatheusAndrade1/Digital-Clock-in-VHDL

Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.

Language: VHDL - Size: 1.28 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0