JayKaku/HDL-Bits-Solutions

HDL Bits solution

Language: Verilog - Size: 50.8 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

lironmiz/nand2tetrisCourse

acadamic course in campus il about building a modern computer from basic logic gates such as "nand" to a general computer architecture that is designed execute any program such as "Tetris". and also building assambler

Language: Scilab - Size: 101 KB - Last synced at: 6 days ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

FaithGriffin/CSARCH1_HDLProject2

Verilog structural model HDL program

Language: Verilog - Size: 119 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject3

Verilog structural model HDL program

Language: Verilog - Size: 109 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject1

Verilog behavioral model HDL program

Language: Verilog - Size: 59.6 KB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

DariodAbate/Logic-Circuits-Project-2022

Hardware component that performs a convolutional encode

Language: VHDL - Size: 1.27 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

sohelrana-aiub/Field-Programmable-Gate-Array-FPGAs

Digital Design with System(Verilog HDL,VHDL , System Verilog & FPGAs)

Size: 112 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

abiduzz420/nand2tetris

building a computer

Language: Assembly - Size: 51 MB - Last synced at: 12 months ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0

achakraborty2591/Learn-SystemVerilog

This repository contains the source files for the SystemVerilog Documentation Website

Language: JavaScript - Size: 357 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

gvilardefarias/Hardware-Data-Structures

A systemverilog implementation of the data structures: priority queue, queue and stack

Language: SystemVerilog - Size: 9.77 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 2 - Forks: 1

Daymorelah/vendingMachine

A simple VHDL code that describes the hardware needed to implement a vending machine

Language: VHDL - Size: 485 KB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

maehw/wokwi-lookup-table-generator

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

Language: Python - Size: 61.5 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 1

miltosmac/TCAD

An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs

Language: C++ - Size: 246 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

rishabh-panda/VLSI-Laboratory

Design and Testbench codes.

Language: Verilog - Size: 396 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

Language: Verilog - Size: 52.7 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1

UFESL/.github

Introduction about Embedded systems lab, University of Florida

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harshbhosale01/HDLBits

In this repository, I will be adding my solutions to HDLBits practice problems

Language: Verilog - Size: 4.88 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

yh08037/Verilog-HDL

[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리

Language: Verilog - Size: 3.91 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

Mehrdadghassabi/Monkey_Cpu 📦

This is a simple CPU descripted in vhdl.

Language: VHDL - Size: 632 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1

AhmadrezaHadi/MIPS-Architecture-Using-Verilog

FPGA Final Project

Language: C - Size: 1020 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

maxkl/hdl-compiler

Compiler for a self-invented hardware description language (mirrors https://gitlab.com/maxkl2/hdl-compiler)

Language: Rust - Size: 201 KB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

diegolrs/Vending-Machine Fork of mthonorio/Vending-Machine

Projeto Final da Disciplina de Circuitos Lógicos II em Verilog usando a IDE do Quartus II

Size: 1.69 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

feliposz/nand2tetris

Exercises and notes on the course Build a Modern Computer from First Principles

Language: Hack - Size: 767 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 1

Mehrdadghassabi/Dosage_cpu Fork of ZahraAbtahi/Dosage-Cpu

dosage is a 20bit single cycle RISC cpu based on harvard architecture

Language: Python - Size: 1.2 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

LorenzoServolini/Minimum-voltage

Description and synthesis (Register-transfer level) of hardware that takes three voltages as input via A/D converters (using the soc/eoc handshake) and returns the minimum value to the consumer using dav/rfd handshake.

Language: Verilog - Size: 21.5 KB - Last synced at: 7 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

ClecioJung/ADC0832-VHDL

Communication of a CPLD with the analog-to-digital converter ADC0832 (modeled in VHDL)

Language: VHDL - Size: 26.4 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

Sh3b0/FPGA-Snake

7-segment snake using a microcontroller

Language: SystemVerilog - Size: 6.86 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

nathsou/hdl

Hardware Description (and Simulation) Library

Language: TypeScript - Size: 1.13 MB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

shivamsingha/hardware-lab-verilog

Verilog sources for Hardware Lab Assignments

Language: Verilog - Size: 294 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

mateusxxlima/hardware-description

Hardware description project in verilog language implemented in the area of Digital Systems in the third semester of the Computer Science course at UFFS

Language: Verilog - Size: 1.95 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

gholomia/Freeman

The digital design of computer systems course project, named freeman with respect to the Ross Freeman, the inventor of FPGA, under supervision of Dr. M. Saheb Zamani.

Language: VHDL - Size: 21.2 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 1

NicolasPR-BR/hdlbitsSolutions

My solutions to HDLBits — Verilog Practice

Language: Verilog - Size: 6.84 KB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

estradjm/Code-Portfolio

Code Portfolio -- Collection of Interesting CS and ECE Projects in different languages (C, C++, Python, CPU & GPU Parallel Paradigms, MATLAB, and VHDL) and target hardware with technical reports, and my Vim Config

Language: C - Size: 146 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 1

InvincibleJuggernaut/ALU

Design for 4 bit ALU with essential logical and arithmetic modules.

Language: Verilog - Size: 1.11 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

EnricoRuggiano/stm32-watchdogs

Language: SystemVerilog - Size: 31.3 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

YeahNotSewerSide/RustyGates

Library for writing and simulating hardware in Rust

Language: Rust - Size: 6.84 KB - Last synced at: 21 days ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

jricaldi95/DAS

VHDL video game and examples of drivers dumped on Spartan3 FPGA

Language: C - Size: 4.39 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

denishoornaert/SimpleSoftcoreArchitecture

Language: VHDL - Size: 815 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

jamestiotio/ehp

SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project

Language: Python - Size: 31.5 MB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

DavidDevoogdt/Brainfuck-CPU

Verilog implementation of Brainfuck cpu

Language: PLSQL - Size: 3.96 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

Razer6/iverilog Fork of steveicarus/iverilog

Icarus Verilog

Language: C++ - Size: 21.3 MB - Last synced at: 10 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

BasRizk/Tic-Tac-Toe-On-FPGA

A Tic-Tac-Toe with multiple level levels and flashing lights implementation using Hardware Definition Language (Verilog) and DE10-Lite Altera Max 10 FPGA.

Language: SystemVerilog - Size: 6.73 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 0 - Forks: 1

rajat2004/Computer-Systems-Design

Language: Scilab - Size: 29.3 KB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

jackrosenthal/schdl

A Scheme Inspired Hardware Description Language

Language: Python - Size: 8.79 KB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 1 - Forks: 0

mLuby/logic-gates

A Hardware Description Language for logic gates interpreted by js

Language: JavaScript - Size: 3.91 KB - Last synced at: 22 days ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0