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GitHub topics: fpga-soc

avlad98/Hybrid_CPU_FPGA_DisertationProject

[Disertation Project] Hybrid CPU and FPGA image processing on a Zybo Z7-10 SoC (Zynq7000) from Xilinx

Language: VHDL - Size: 267 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

fmhess/fmh_gpib_core

GPIB IEEE 488.1 core

Language: VHDL - Size: 511 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 18 - Forks: 8

peacekeeper228/labHPS

working with HPS

Language: C - Size: 17.6 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 0

AhmedERady/Grad_Project

Smart Automation Controller for Precision Agriculture

Language: V - Size: 124 MB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

splinedrive/lets_build_a_compiler_for_riscv

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

Language: C - Size: 2.65 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 21 - Forks: 4

Goshik92/multicore-nios

Matrix multiplication on multiple Nios II cores

Language: C - Size: 399 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 11 - Forks: 6

daniel-santos-7/leaf

Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

Language: VHDL - Size: 660 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 3 - Forks: 3

mohamedtareq24/ODE_solver_NIOS_II

NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA

Language: Verilog - Size: 884 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

peacekeeper228/multi-core-processor

Upgrade of SchoolMIPS single-core processor

Language: Verilog - Size: 3.91 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 7 - Forks: 0

MEVIUS-FPT/hls_traffic_light_recognition

Traffic Light Recognition with High-Level Synthesis

Language: C++ - Size: 22.5 KB - Last synced at: 6 days ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 2

nhasbun/de10nano_fpga_linux_config

DE10-Nano FPGA Configuration from Linux. Software to configure the FPGA portion of the Cyclone V SoC.

Language: C - Size: 8.79 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 21 - Forks: 6

ustb-owl/TinyMIPS

The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.

Language: C++ - Size: 31.6 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 31 - Forks: 6

duclos-cavalcanti/microsemi-error-detection

Error Correction and Detection using Microsemi's SmartFusion2 Kit, FPGA, SoC

Language: C - Size: 35.1 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Divyathali/FPGA-Routing-placement---Best-way

The published IEEE paper tells about the basic details of this project

Language: C - Size: 102 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0

ikwzm/FPGA-SoC-U-Boot-PYNQ-Z1

U-Boot image for PYNQ-Z1

Language: Shell - Size: 1.34 MB - Last synced at: 5 days ago - Pushed at: about 7 years ago - Stars: 4 - Forks: 1

KastnerRG/infinitam_fpga

InfiniTAM on FPGA

Language: C++ - Size: 6.28 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 23 - Forks: 2

Koyama-Tsubasa/VLSI_System_Design

Coursework of NTHU CS512000 VLSI System Design

Language: C - Size: 20.2 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

Nathen-Smith/FPGA-super-mario-bros

FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

Language: Verilog - Size: 1.02 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 2

mcagriaksoy/VHDL-FPGA-LAB_PROJECTS

My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)

Language: VHDL - Size: 575 KB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 14 - Forks: 2

avikram2/PacmanFPGA

ECE 385 Final Project on DE-10 FPGA Board with NIOS 2 SoC: Implementing PacMan

Language: Verilog - Size: 482 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mcci-catena/catena-riscv32-fpga

RISC-V 32-bit core for MCCI Catena 4710

Language: Verilog - Size: 114 KB - Last synced at: almost 2 years ago - Pushed at: almost 6 years ago - Stars: 8 - Forks: 2

snyderth/SCARA_robot

A SCARA topoology robotic arm

Language: Python - Size: 390 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

messes2/ECE-385-Final-project

I made a motion controlled digital synthesizer known as a puppeteer theremin that uses AI to get motion control data from a server hosted on a phone onto an FPGA.

Language: SystemVerilog - Size: 9.49 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

falsestatement/GeoDashFPGA

This is a very basic replication of the popular rhythm / platformer game Geometry Dash, implemented completely in hardware through System Verilog

Language: Verilog - Size: 34.4 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

pedrovt/cr-labs

Labs of the Reconfigurable Computing course, University of Aveiro

Language: VHDL - Size: 108 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 1

kodachi77/DE10liteDhrystone

Nios II Embedded System Dhrystone Test

Language: C - Size: 1.31 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

raetro/raetro_system_kernel

Rætro Linux Kernel Source

Language: C - Size: 218 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

ugoleone/zedboard_image_processing_pipeline

FPGA based image processing pipeline using zedboard, able to accelerate openCV functions

Language: VHDL - Size: 152 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 8 - Forks: 1

NukaCola-Quantum/MBIST-verilog

A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated

Language: Verilog - Size: 22.5 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 7 - Forks: 2

khldunsaid/Designed-and-Implemented-a-multicore-processor-using-FPGA.

This project aims to learn how to perform hardware-software co-design of an FPGA-based multi-core processor system and parallelize applications to the multi-core processor and optimize the performance using various techniques.

Language: C - Size: 80.1 MB - Last synced at: 12 months ago - Pushed at: almost 4 years ago - Stars: 6 - Forks: 1

HuangDave/MIPS

Single-Cycle and 5-stage Pipelined SoC

Language: Verilog - Size: 44.3 MB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

Stuart0l/BNN

HLS code for a BNN accelerator

Language: C++ - Size: 2.31 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 10 - Forks: 7

wubinary/two_stream_soc

SOC of two_stream action recognition on ZCU102

Language: Jupyter Notebook - Size: 35.7 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 1

kelhuynh/MECHTRON-3TB4-Labs

3TB4-Embedded Systems II

Language: SystemVerilog - Size: 90.1 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

ZipCPU/s6soc

CMod-S6 SoC

Language: Verilog - Size: 2.8 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 33 - Forks: 5

nhasbun/uart_core_lib

Driver - Library for C applications using Altera's UART Core through Avalon Bus on Cyclone V.

Language: C - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 3

nhasbun/uart_16550_core_lib

Altera wrappers for C applications using Altera's 16550 UART Core through Avalon Bus on Cyclone V.

Language: C - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 2

JoseDavidSS/CE_Architecture1.ASIP-Image_Interpolation Fork of juanignava/ComputerArchitecture1.Project2

Segundo proyecto para el curso de Arquitectura de Computadores. La idea es hacer un ASIP (Application Specific Set Processor) que genere interpolación de imagen por medio de un compilador, código en ensamblador, un procesador pipeline y scripts en alto nivel.

Language: Python - Size: 60.1 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

cajt/cmod-a7-35t_leon3

GRLIB GPL support for Digilent CMOD A7 35T board

Language: VHDL - Size: 2.2 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 1

richardbenstead/ebaz4205

Projects using ebaz4205 Zynq board

Language: HTML - Size: 495 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

jonakor/ZedBoard_prototyping

Hardware .tcl code and software .c code for ZedBoard prototyping

Language: C - Size: 71.3 KB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

fmhess/fmh_framebuffer

A VHDL rotating framebuffer with an Avalon ST Video output.

Language: VHDL - Size: 61.5 KB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 1

sdonchez/petalinux-zedboard-test

A simple proof of concept project demonstrating the use of PetaLinux in conjunction with Vivado to deploy a Linux environment alongside programable logic on a heterogeneous System on a Chip (SoC).

Language: HTML - Size: 664 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

davemuscle/camera_journey

Various lessons learned while designing an OV5640 camera display in VHDL/Embedded Linux on a Cyclone V SOC board

Language: VHDL - Size: 53.9 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

nmigen1/nmigen-soc

nmigen-soc - System on Chip toolkit for nMigen - MIRRORED - https://gitlab.com/nmigen/nmigen-soc/

Language: Python - Size: 126 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

HaydenGoodfellow/ECE241

Projects from a second-year computer engineering course on digital logic (written in Verilog)

Language: Verilog - Size: 40.3 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

Gabriele-bot/PYNQ_IA

Repository that contains some neural network inferences on PYNQ-Z2 board employing hls4ml

Language: Ada - Size: 233 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

ismailfaruk/ECSE324--Computer-Organization

Academic projects created using Assembly, in the Intel FPGA Monitor Program, for the laboratory work done while attending the McGill Course ECSE 324 Computer Organization

Language: Assembly - Size: 8.95 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 3

Goshik92/fsearch

FastSearch is a project intended to increase the speed of string searching by using the FPGA technology

Language: Verilog - Size: 28 MB - Last synced at: over 2 years ago - Pushed at: almost 7 years ago - Stars: 5 - Forks: 3

cmcquinn/replicookie

A 3D printer controller board based around the Snickerdoodle development board.

Language: Shell - Size: 13.1 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

ikwzm/FPGA-SoC-U-Boot-DE0-Nano-SoC

U-Boot image for DE0-Nano-SoC

Language: Shell - Size: 329 KB - Last synced at: 5 days ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 1

fast-codesign/FAST-OpenBox-S4

FAST implemented on Xilinx Zynq7000 SoC board

Language: Makefile - Size: 16.7 MB - Last synced at: about 2 years ago - Pushed at: almost 5 years ago - Stars: 12 - Forks: 5

0xD503/Digital-music-project

Laboratory work project

Language: SystemVerilog - Size: 196 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

AbedYassine/ece1373mclightprop

A MonteCarlo light propagation algorithm on a Xilinx FPGA using High Level Synthesis.

Language: C - Size: 2.89 MB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 0 - Forks: 0

htanwar922/VHDL-Numerical-Overcurrent-Relay

Fixed and float packages. Overcurrent relay.

Language: VHDL - Size: 80.1 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

jagkush/ZYNQ_based_traffic_light_controller

A final project for FPGA_SOC course

Language: HTML - Size: 34.8 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

pedrovt/cr-square-root-cop

A FPGA Based Square Root Approximation Coprocessor

Language: VHDL - Size: 220 MB - Last synced at: almost 2 years ago - Pushed at: almost 5 years ago - Stars: 1 - Forks: 1

jarios86/marex

MAREX: P-System hardware processor

Language: VHDL - Size: 1.51 MB - Last synced at: 3 months ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

HaydenGoodfellow/ECE243

Projects from a second-year computer engineering course on computer organization (written in C, Assembly (ARMv7-A), and Verilog)

Language: Assembly - Size: 21.4 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

mavalderrama/master_thesis_presentation

Master Thesis Presentation LATEX

Language: TeX - Size: 12.3 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

mavalderrama/master_thesis_manuscript

Masters Thesis Manuscript LATEX

Language: TeX - Size: 20.7 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 1

imciner2/cmake-embedded-toolchains

CMake toolchains and files for developing embedded systems, including ARM, FPGA and SoC devices

Language: CMake - Size: 4.88 KB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

micro-FPGA/MEGA65-Hacks

Hacks and non standard things with MEGA65 Computer

Size: 39.1 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 0 - Forks: 0

sgq995/rc4-de0-nano-soc

It's a cryptoprocessor that implements de RC4 algorithm

Language: SystemVerilog - Size: 76.9 MB - Last synced at: 3 months ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 1

0xD503/I2C-Interface

I2C Interface RTL description

Language: SystemVerilog - Size: 3.91 KB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

0xD503/SPI-Interface

SPI Interface RTL Description

Language: SystemVerilog - Size: 1000 Bytes - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0

ikwzm/FPGA-SoC-U-Boot-ZYBO

U-Boot image for ZYBO

Language: Shell - Size: 1.15 MB - Last synced at: 5 days ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

tanmayv25/Microprocessor-System-Design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

Size: 1.1 MB - Last synced at: 9 days ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0