GitHub topics: fpga-programming

Repositories

errray/fpga-spaceship

This space ship game project, where the spaceship is positioned at the center and objects coming from different directions can be hit using FPGA buttons, has been implemented with Verilog coding in quartus environment for Altera System-on-Chip (SoC) FPGA and VGA for display.

Language: Verilog - Size: 656 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

SaBuMa/Juego-Pong-en-VHDL--VHDL-Pong-Game

Juego Pong en VHDL // VHDL Pong-Game

Language: VHDL - Size: 32.9 MB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

AkhilRai28/Single-Port-RAM

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Language: Verilog - Size: 68.4 KB - Last synced at: 1 day ago - Pushed at: 11 months ago - Stars: 3 - Forks: 0

mongshil553/Digital-Engineering-Verilog-Assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

Language: Verilog - Size: 4.88 KB - Last synced at: 5 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

marco-milanesi/FlybackConverter-FPGA-based-Digital-Twin

Repository containing code, libraries, schematics, and 3D models from the paper 'FPGA-Based Digital Twin Implementation for Power Converter System Monitoring.

Language: Verilog - Size: 211 MB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

Sarthak-Singh/Counter-on-7segment-VLSI

A project I made during my training, while learning VLSI. Used Verilog to program the FPGA board's 7 segment display to work as a counter, (configurable in up & down order).

Language: C - Size: 1.09 MB - Last synced at: 11 months ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

Swarup1747/Cache-Compression-Implementation-on-FPGA-using-Verilog-HDL

Cache Compression using Verilog HDL

Size: 82 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

peplxx/Morse-Coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

Language: HTML - Size: 10 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

kk26nav/Verilog-Experiments

Collection of all verilog experiments

Language: Verilog - Size: 562 KB - Last synced at: 12 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

arjunxvaish/Connect-Four

connect four game, Verilog

Language: SystemVerilog - Size: 19.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ATalhaTimur/Micro_CSE4117

special microprocessor design

Language: C - Size: 158 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

cornell-zhang/heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Language: Python - Size: 38.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 320 - Forks: 93

Prithvish04/channel_encoding_veterbi_decoding

Language: HTML - Size: 1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

ARMCoderBR/BenEatersSAP1

A FPGA implementation of Ben Eater's SAP-1 computer using the Digilent's BASYS 3 board.

Language: Verilog - Size: 852 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

cztee/Lattice_iCEStick_SelfStudy_Notes

Language: VHDL - Size: 4.44 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Simple-Nios2-Project

Designing a simple processor system on FPGA. This is demo project to test FPGA DE10-Standard and develop a simpe Nios2 app.

Language: Verilog - Size: 1.37 MB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Project-Nios2-DMA-Accelerator

Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.

Size: 18.6 KB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

SakaSerbia/FPGA-DE10-Standard-Blinking-LED

First FPGA Project done on FPGA DE10-Standard. Simple blinking of LED.

Language: Verilog - Size: 32.2 KB - Last synced at: about 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

tom-zv/FPGA-ESP32-Projects

Projects showcase

Language: VHDL - Size: 287 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

bizkiwi/verilog-fpga-pingpong-game

Design and implementation of an electronic game using Verilog and the Basys3 Field Programmable Gate Array (FPGA) kit.

Language: Verilog - Size: 3.96 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

jgelfman/Dataflow-Based-FPGA-Program-Synthesis-Capstone

An FPGA Program Generator written in Python that takes dsp-sig XML Dataflow Graphs created using FAUST to produce FPGA programs in VHDL.

Language: VHDL - Size: 3.46 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 0

ziyue-pan/FPGA--JOJO

Final project of Digital Logic Design course, a video game.

Language: VHDL - Size: 62.4 MB - Last synced at: 3 months ago - Pushed at: over 4 years ago - Stars: 5 - Forks: 0

codr-void/portfolio.io

Wa'el Engineering Project Repository

Language: Python - Size: 80.7 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

shahed22/Dadda-8-bit

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Language: Verilog - Size: 11.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

wjh776a68/sv_pcie

Simple implementation of PCIE4C-based pcie transfer on Xilinx Ultrascale+ FPGAs

Language: Tcl - Size: 122 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

cornell-zhang/GraphLily

A graph linear algebra overlay

Language: C++ - Size: 117 MB - Last synced at: about 1 year ago - Pushed at: about 2 years ago - Stars: 47 - Forks: 2

robseb/rstoolsA10

Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA

Language: C++ - Size: 1.27 MB - Last synced at: about 2 months ago - Pushed at: about 4 years ago - Stars: 5 - Forks: 2

jash0803/Simple_Elevator_Design

During the EL-203 course, we had to make a elevator controller project under Professor Biswajit Mishra.

Language: Verilog - Size: 2.93 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

NatsuDrag9/ethernet-switch

Design of 4-port gigabit ethernet switch

Language: VHDL - Size: 4.34 MB - Last synced at: about 1 year ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

hajin-kim/FPGA_AXI_and_VHDL

FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain

Language: VHDL - Size: 2.41 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

dineshpinto/timetagger

FPGA programming for nanosecond photon counting

Language: C - Size: 105 MB - Last synced at: 3 months ago - Pushed at: over 3 years ago - Stars: 4 - Forks: 1

Robin329/VerilogThings

Some exercises on verilog.

Language: Verilog - Size: 76.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

7enTropy7/Artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

Language: Verilog - Size: 31.3 KB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 6 - Forks: 3

krish1925/Logic-Design-Verilog

Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module

Language: Tcl - Size: 8.53 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

benitoss/ZXDOS

Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines

Language: VHDL - Size: 55.2 MB - Last synced at: 3 months ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 0

rv2442/16BitScientificCalculator

16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board

Language: C - Size: 961 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 2

styczynski/fpga-verilog

Collection of my projects that was made as a part of Warsaw University FPGA course

Language: Verilog - Size: 441 KB - Last synced at: about 2 months ago - Pushed at: over 6 years ago - Stars: 6 - Forks: 0

JN513/estudos_verilog

Exemplos feito em verilog para estudos

Language: Verilog - Size: 10.6 MB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

zahi1/Digital-Electronics

Digital Electronics repo includes Boolean algebra and logic circuit design, covering topics such as gates, combinational and sequential circuits. It will help you learn logical circuit design principles, analyze circuits using automated tools, and delve into VHDL coding for the design and implementation of digital circuits on FPGA devices.

Size: 2.42 MB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Ineso1/VerilogModules

A collection of educational and practical Verilog modules for FPGA design, tested on Delite FPGA MAX 10 with Intel Quartus and ModelSim. Includes utilities like Clock Dividers, Debouncers, Decoders, State Machines, and more.

Language: Verilog - Size: 254 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Raveem13/HDLbits-practice-solution

This is a repository containing my solutions to the problem statements given on HDLBits website.

Language: Verilog - Size: 150 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

GraceSevillano/RTIC-project-Antoine-s-army

This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed

Language: VHDL - Size: 12.3 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

raetro/sdk-docker-fpga

Intel Quartus Prime Synthesis Engine for Docker

Language: Dockerfile - Size: 847 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 31 - Forks: 7

Davide-Ettori/Memory_Interaction-Hardware-Component-FPGA

Digital Circuits Design Project (PoliMi, year 2022) - Memory Interaction

Language: VHDL - Size: 7.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

KayeJD/NexysA7-FPGA-Programming

Embedded Programming Projects

Language: Tcl - Size: 56.6 KB - Last synced at: 4 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

fm16191/fpga-vector-add

vector-add scripts using oneAPI and targeting FPGA devices. Verifications made on Intel's devcloud.

Language: C++ - Size: 44.9 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

kocatepedogu/cellular-automaton-processor

A simple processor with a grid of cores that can only interact with their immediate neighbors

Language: SystemVerilog - Size: 211 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Mesbah-Lab-UCB/DNN_MPC_Plasma_FPGA

Project files for a neural network (NN) implementation on an FPGA using Vivado HLS.

Language: Verilog - Size: 3.01 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

n-roussos/A-framework-for-developing-Neural-Networks-in-hardware-accelerators Fork of georgevangelou/A-framework-for-developing-Neural-Networks-in-hardware-accelerators

This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.

Language: C - Size: 25 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

aslak3/spi-flasher

Pi Pico based SPI flash flasher

Language: C - Size: 15.6 KB - Last synced at: 7 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

gaikwadabhishek/flappy-bird-fpga-vhdl

Flappy Bird on FPGA using VHDL

Language: HTML - Size: 119 KB - Last synced at: 3 months ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

narajoEmmanuel/Millisecond-Counter-Circuit

Language: Verilog - Size: 1.02 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cnsl-mru/StocNoC-Accelerating-Stochastic-Models-Through-Reconfigurable-Network-on-Chip-Architectures Fork of dsdnu/sisNoC

Reconfigurable network on chip architecture for accelerating stochastic models

Language: VHDL - Size: 14.2 MB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

KatelynLam97/-Digital-Systems-Project-Microwave

Size: 84 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

hajin-kim/FPGA_Tutorial_with_HLS

FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS

Language: Tcl - Size: 4.41 MB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 0

cucapra/polyphemus

A Cyclops managing FPGA execution in the clouds

Language: Python - Size: 295 KB - Last synced at: about 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2

skrevolve/FPGA

FPGA learning course

Size: 4.88 KB - Last synced at: about 2 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

PauloMaced0/Washing_machine

Washing machine simulation using an FPGA

Language: VHDL - Size: 3.25 MB - Last synced at: about 1 year ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

talhasevinc/FPGA

FPGA Digital Hardware Design

Language: VHDL - Size: 74.5 MB - Last synced at: about 1 year ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

mukullokhande99/fifo_hardware_fpga

FIFO implemented on FPGA Spartan 6

Language: Rich Text Format - Size: 21.4 MB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 1

AtlasFPGA/MULTICORE-ESdUDO-ROJO

Diseñar la placa - ¡Créalo tu mismo! De coste más reducido para la Fpga CYC1000, con una BLUEPILL STM32F103C8T6

Size: 22.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

aybaras/VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Language: VHDL - Size: 494 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 2

jjgar11/Digital-2

Desarrollo para la materia de Electronica Digital 2

Language: Verilog - Size: 15.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

amaranth-farm/amaranth-boards Fork of amaranth-lang/amaranth-boards

Up-to-date board and connector definition files for amaranth HDL

Language: Python - Size: 298 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 1

algorhtym/booths_multiplier

Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method

Language: VHDL - Size: 6.84 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Tauheed-Elahee/FPGA-Stopwatch

Impement a simple stopwatch on an FPGA. There is an added goal of making as many modules paramterized as possible and sticking to structural code as much as possible.

Language: Verilog - Size: 255 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

matthewyjiang/fpga-blind-maze

EE354 (Intro to Digital Circuit Design) - Final Project by Matthew Jiang and Kelvin Cao

Language: Verilog - Size: 70.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Hello-FPGA/BISS-C

This is BISS-C FPGA IP and It's Driver Repo

Language: Tcl - Size: 4.85 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

Mohamed-Adil-Cyber/FPGA_CycloneIV_ep4ce6e22c8n_Electrical_Pulse

Simple electrical pulse preferably for LEDs made for cyclone IV with image examples

Language: VHDL - Size: 262 KB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 2 - Forks: 0

TinyRetroWarehouse/Awesome-Retro-Docs

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Size: 13.8 GB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 142 - Forks: 18

santifs/simon-game-vhdl

VHDL game that displays incremental random sequences on an LED Matrix by creating a finite state machine and implementing RAM and ROM models.

Language: VHDL - Size: 7.94 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

santifs/ultrasonic-sensor

Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.

Language: VHDL - Size: 6.83 MB - Last synced at: over 1 year ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2

bilalkabas/Basys3-VHDL-Basics

This repository has basic examples in VHDL using Basys3 board.

Language: VHDL - Size: 39.1 KB - Last synced at: about 1 year ago - Pushed at: almost 5 years ago - Stars: 7 - Forks: 5

alibukharai/embedded_system

This repository is primarily designed for my personal learning, featuring small projects and demonstration code based on ESP-32 and STM-32 platforms. Its main focus revolves around Real-Time Operating Systems (RTOS) and CPU architecture exploration.

Language: C - Size: 163 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

ngrabbs/arm_projects

ARM single cycle processor on nandland.com go-board

Language: SystemVerilog - Size: 20.9 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

akangakang/OS-ChCore-Lab

上海交通大学软件学院🍭操作系统课程🍦实验

Language: C - Size: 38.5 MB - Last synced at: about 1 year ago - Pushed at: about 4 years ago - Stars: 20 - Forks: 12

Marslanali/fpga_vertex_6_gtx_Interface 📦

Vertex 6 FPGA GTx Transciever Simulation in Xilinx ISE using Xilinx IP Core

Language: Verilog - Size: 10.4 MB - Last synced at: over 1 year ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

ibrahimalimetin/Robotic-Controller-with-FPGA

Robotic Controller with FPGA

Language: VHDL - Size: 563 KB - Last synced at: over 1 year ago - Pushed at: about 4 years ago - Stars: 3 - Forks: 0

jamarma/Mecatronica-proyecto

Robot educativo con forma de araña impreso en 3D y controlado a través de una FPGA

Size: 311 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 6 - Forks: 1

10x-Engineers/Infinite-ISP_Firmware

Infinite-ISP Image Signal Processing Pipeline Firmware for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit (coming soon).

Size: 9.77 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cp024s/100-days-of-RTL

probable journey of RTL coding ft. Chandra Prakash

Language: Verilog - Size: 292 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

DidierMalenfant/openFPGA-tutorials

A collection of tutorials and resources for the openFPGA platform.

Size: 2.68 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 0

DericAugusto/ISN2023_DigitalSystems

Material from the course of Design of Digital Systems at ENSEM - Université de Lorraine.

Language: VHDL - Size: 40.8 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

abdalla1912mohamed/-AES-encryption-and-decryption-platform-in-FPGA-communication

implementing a protected communication platform between 2 FPGA's. Data is entered through a keyboard-FPGA interface then the data is encrypted using AES encryption and sent to the second FPGA where the decryption occurs if the decryption key is given and the data is displayed using an FPGA-LCD interface using VHDL scripts

Language: C - Size: 1.14 MB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

z4chh/FPGA_Slot_Machine

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.

Language: SystemVerilog - Size: 12.7 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

einstein07/Vivado-IP-and-Resource-Usage

Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

Language: VHDL - Size: 12.8 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

tiagosr/gategen

Racket-based hardware definition DSL for generating gateware for FPGAs, ASICs and the like

Language: Racket - Size: 16.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

madmaverickminion/Soil-monitoring-bot

This repository contains all the work(till task 5) of Soil Monitoring Bot theme(eYRC-2021-22).

Language: Verilog - Size: 26.7 MB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

ArnaudPoletto/epfl-cs208-tetris-project

Experience the classic arcade game in a whole new way! Play Tetris in Assembly and master the art of arranging falling blocks. Challenge your reflexes and strategic thinking in this nostalgic journey. Ready to achieve new high scores? Let the Tetris frenzy begin! 🎮🧱

Language: Assembly - Size: 8.79 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0