damian95a/Analog-signal-generator

FPGA based analog signal generator with DAC

Language: Verilog - Size: 461 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

AzazHassankhan/FPGA-IntelligenceSuite

Welcome to the "Machine Learning Models FPGA" repository! 🌟This project showcases the fusion of cutting-edge machine learning techniques with the power of Field-Programmable Gate Arrays (FPGAs). Our goal is to harness the capabilities of FPGA hardware to accelerate and optimize machine learning model deployment.

Language: Jupyter Notebook - Size: 33.4 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

d953i/Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

Language: Tcl - Size: 28.6 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 28 - Forks: 17

2uger/petalinux_notes

Language: SystemVerilog - Size: 10.7 KB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 2 - Forks: 0

dariusur/SpectrumAnalyzer

FPGA-based real-time audio spectrum analyzer.

Language: VHDL - Size: 54.8 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

li3tuo4/rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

Language: Tcl - Size: 79.9 MB - Last synced: 3 months ago - Pushed: about 1 year ago - Stars: 50 - Forks: 15

Jrvvv/simple-risc-v-cpu

Developing RISC-V CPU

Language: SystemVerilog - Size: 531 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

yaxsomo/IRIS_CubeSat

This Repository is dedicated to FPGA development of the IRIS CubeSat

Language: VHDL - Size: 88.4 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

giuseppericcio/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102 Fork of LaErre9/Zynq_Ultrascale_Vitis_AI_CNN_ZCU102

Workflow for executing CNN Networks on Zynq Ultrascale+ with Vitis AI toolchain. Detailed analysis, configuration and execution of Convolutional Neural Networks on ZCU102 using Vitis AI, evaluating performance on the board compared to Cloud infrastructure (eg. Kaggle). Developed for educational exam purposes.

Language: Jupyter Notebook - Size: 252 MB - Last synced: about 2 months ago - Pushed: about 2 months ago - Stars: 1 - Forks: 0

Layheng-Hok/Digital-Piano

Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100

Language: Verilog - Size: 9.96 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 0

gubbriaco/FPGA-VHDL-Wallace-multiplier

Design and Analysis of an FPGA-based Wallace Multiplier.

Language: Jupyter Notebook - Size: 12.2 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

cas-mls/cpu2

his is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.

Language: VHDL - Size: 58 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

Teddy-van-Jerry/sdr-psk-fpga

Dual-Mode PSK Transceiver on SDR With FPGA

Language: Verilog - Size: 281 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 3 - Forks: 2

jge162/ScoreBoard-wTimer

Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.

Language: Verilog - Size: 2.38 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 23 - Forks: 7

briansune/Kintex-7-OV4689-Verilog

Xilinx Kintex-7 based OV4689 MIPI Camera Example

Size: 77.9 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 2 - Forks: 0

siorpaes/BareBonesCortexM0

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

Language: Verilog - Size: 106 KB - Last synced: 5 months ago - Pushed: over 5 years ago - Stars: 19 - Forks: 9

der-mur/zynq-cpp-sandbox

This is my sandbox for exploring the use of C++ to develop projects for the AMD (Xilinx) Zynq. One of the aims is to begin the process of creating a range of c++ drivers that can be re-used for other Zynq-7000/Ultrascale/Microblaze designs. The IDE is Vivado/Vitis 2023.2 (Classic version).

Language: HTML - Size: 34 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

erwanregy/Neural-Network-on-an-FPGA

Implements a fully connected dense neural network in SystemVerilog, synthesisable to an FPGA for neural network computation acceleration

Language: SystemVerilog - Size: 3.1 MB - Last synced: 5 months ago - Pushed: about 1 year ago - Stars: 0 - Forks: 0

der-mur/zynq-freertos-sandbox

This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.

Language: C - Size: 32.8 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

AzazHassankhan/VHDLCodeCraft

Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐

Size: 182 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 1 - Forks: 0

RedBlaze42/FPGA-VHDL-TrafficLights

This program implements a traffic light state machine on the Basys 3 development board. The traffic light consist of a RED, YELLOW and GREEN LEDs for the car lights and a RED and GREEN LEDs for the pedestrian ligths.

Language: Tcl - Size: 3.19 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

MJoergen/Avalon

Utilities for Avalon Memory Map

Language: VHDL - Size: 977 KB - Last synced: 2 months ago - Pushed: 4 months ago - Stars: 5 - Forks: 0

Hibiki33/Intelligent-Architecture

Intelligence Computing Architecture of BUAA.

Language: Verilog - Size: 315 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

meiniKi/logIP

Logic Analyzer IP Core

Language: SystemVerilog - Size: 306 KB - Last synced: 4 months ago - Pushed: almost 2 years ago - Stars: 3 - Forks: 0

pawel2000pl/VerilogLedDriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

Language: Tcl - Size: 1.91 MB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 0 - Forks: 0

patrickleboutillier/jcscpu-hw

Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".

Language: Verilog - Size: 268 KB - Last synced: about 2 months ago - Pushed: almost 4 years ago - Stars: 12 - Forks: 3

kayas257/DHT11-zynq

Zynq Design Example

Language: VHDL - Size: 32.2 KB - Last synced: 5 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

MatthieuMichon/fpga

FPGA related repo

Language: VHDL - Size: 812 KB - Last synced: 6 months ago - Pushed: over 4 years ago - Stars: 0 - Forks: 0

plunify/InTime-Vivado

Useful scripts to run and configure InTime with the Xilinx Vivado tools.

Language: Verilog - Size: 179 KB - Last synced: 6 months ago - Pushed: over 2 years ago - Stars: 0 - Forks: 0

ngiambla/qvmi

Quick Verilog Module Isolator - Isolates a design for testing.

Language: Verilog - Size: 233 KB - Last synced: 6 months ago - Pushed: over 5 years ago - Stars: 3 - Forks: 0

pavel-demin/eclypse-z7-notes

Notes on the Eclypse Z7 development board

Language: C - Size: 387 KB - Last synced: 2 months ago - Pushed: 2 months ago - Stars: 9 - Forks: 2

XAli-SHX/FPGA-Implementation-of-Image-Processing-for-MNIST-Dataset-Based-on-CNN-Algorithm

FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)

Language: VHDL - Size: 64.9 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 4 - Forks: 0

lazuardinfl/Tic-tac-toe-FPGA

Tic-Tac-Toe with SoC FPGA

Language: VHDL - Size: 25.3 MB - Last synced: 6 months ago - Pushed: almost 3 years ago - Stars: 0 - Forks: 0

FPGA-Systems/spi-mpc3201

Different SPI implementation

Language: Verilog - Size: 26.4 KB - Last synced: 6 months ago - Pushed: over 3 years ago - Stars: 3 - Forks: 2

Nurhak/VivadoTutorial

Size: 18.9 MB - Last synced: 6 months ago - Pushed: over 5 years ago - Stars: 0 - Forks: 0

pos3id0nas/Epanadiamorfosima-VHDL-Code-with-TB

Language: Tcl - Size: 6.8 MB - Last synced: 6 months ago - Pushed: over 2 years ago - Stars: 1 - Forks: 0

bence1995/snake

Snake game implementation on Kintex-7 devboard

Language: VHDL - Size: 34.1 MB - Last synced: 6 months ago - Pushed: over 5 years ago - Stars: 1 - Forks: 0

avijeet-trivedi/Connect6

Connect6 Game Solver

Language: C - Size: 118 KB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 0 - Forks: 0

lauchinyuan/FPGA_QPSK-modem

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

Language: Verilog - Size: 15.5 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 24 - Forks: 7

aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

Language: TeX - Size: 191 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 1 - Forks: 0

Dhruv0Upadhyay/100_Days_of_RTL

100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog

Language: Verilog - Size: 1.05 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 3 - Forks: 0

mwrnd/innova2_mnv303611a_xcku15p_xdma

XDMA PCIe to BRAM and GPIO demo for the XCKU15P FPGA on the Innova-2 Flex Open VPI MNV303611A-EDLT and MNV303212A-ADLT

Language: Tcl - Size: 3.17 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

mwrnd/innova2_xdma_demo

Innova2 XCKU15P XDMA PCIe Demonstration Starter Project

Language: Tcl - Size: 9.11 MB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 0 - Forks: 1

vborchsh/make-fpga

Set of scripts for Vivado's project handling

Language: Tcl - Size: 35.2 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 5 - Forks: 0

vogma/neorv32-arty-ddr-setup

A simple NEORV32 setup utilizing the DDR3 Memory of an Arty A7 100T FPGA Board

Language: Tcl - Size: 97.7 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 0 - Forks: 0

multigcs/FPGA-blinky

Language: Makefile - Size: 90.8 KB - Last synced: 4 months ago - Pushed: 4 months ago - Stars: 3 - Forks: 1

ilaydayaman/CNN_for_SLR

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

Language: Verilog - Size: 21.5 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 79 - Forks: 30

jofrfu/tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Language: VHDL - Size: 1.42 MB - Last synced: 7 months ago - Pushed: over 5 years ago - Stars: 309 - Forks: 59

carlesfernandez/docker-petalinux

Docker image generation for Xilinx Petalinux Tools and Vivado

Language: Dockerfile - Size: 130 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 6 - Forks: 7

Pedroo64/XtrRiscv

Language: VHDL - Size: 455 KB - Last synced: 25 days ago - Pushed: 25 days ago - Stars: 2 - Forks: 0

bilalkabas/Basys3-VHDL-Basics

This repository has basic examples in VHDL using Basys3 board.

Language: VHDL - Size: 39.1 KB - Last synced: about 1 month ago - Pushed: almost 4 years ago - Stars: 7 - Forks: 5

DvvCz/CPE-133

Language: SystemVerilog - Size: 27.3 KB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 1 - Forks: 0

iDoka/eda-scripts

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

Language: Shell - Size: 215 KB - Last synced: 7 months ago - Pushed: 8 months ago - Stars: 20 - Forks: 1

mvsoliveira/IBERTpy

A Python package for running IBERT Eye scan in Vivado, ploting eye diagrams with mathplotlib and compiling results with LaTeX

Language: Python - Size: 98.3 MB - Last synced: 8 months ago - Pushed: almost 3 years ago - Stars: 11 - Forks: 4

vinayak1998/Multiplier-Design

Language: VHDL - Size: 1.16 MB - Last synced: 8 months ago - Pushed: over 6 years ago - Stars: 1 - Forks: 0

vinayak1998/Reflex-Tester

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

Language: VHDL - Size: 1.02 MB - Last synced: 8 months ago - Pushed: over 6 years ago - Stars: 4 - Forks: 0

zhouxingkong/HuffmanCoding

对{0~9}数字进行霍夫曼编码（HuffmanCoding）的verilog程序，编码只用9个时钟周期

Language: Verilog - Size: 10.7 KB - Last synced: 8 months ago - Pushed: over 6 years ago - Stars: 3 - Forks: 2

Luke7412/IpLibrary

Library containing various VHDL IPs

Language: SystemVerilog - Size: 486 KB - Last synced: 5 months ago - Pushed: 5 months ago - Stars: 4 - Forks: 0

ManishPatla/QuantumComputation_FPGAs

Emulating Quantum Circuits on FPGAs

Size: 8.91 MB - Last synced: 7 months ago - Pushed: 7 months ago - Stars: 1 - Forks: 0

changwoolee/lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

Language: C++ - Size: 105 MB - Last synced: 7 months ago - Pushed: over 2 years ago - Stars: 262 - Forks: 85

wyattduber/CyDAQ

CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy

Language: C - Size: 984 MB - Last synced: 6 months ago - Pushed: 6 months ago - Stars: 2 - Forks: 0

junwha0511/MNIST-FPGA-Accelarator

MNIST accelerator using pynq-z2 and the binary qunatization

Language: C++ - Size: 13.4 MB - Last synced: 7 months ago - Pushed: over 1 year ago - Stars: 9 - Forks: 1

HYSUM-TOBBETU/AES-Encryption-Verilog-Pipelined-Implementation-128bit

Device: Zedboard xc7z020clg484-1, Clock Rate: 319 MHz, Tool: Vivado 2018.3, Language: Verilog

Language: Verilog - Size: 66.1 MB - Last synced: 4 months ago - Pushed: over 3 years ago - Stars: 7 - Forks: 0

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

Language: VHDL - Size: 46.9 KB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 2 - Forks: 1

UCLA-VAST/RapidStream

[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

Language: Python - Size: 142 MB - Last synced: 7 months ago - Pushed: over 1 year ago - Stars: 103 - Forks: 18

wyu0725/SDHCAL_DAQ

New SDHCAL DAQ Workspace

Language: VHDL - Size: 3.71 GB - Last synced: 8 months ago - Pushed: over 4 years ago - Stars: 1 - Forks: 5

mattuna15/merlin

Learn how to create your own 32-bit system from scratch.

Language: Assembly - Size: 19 MB - Last synced: 2 months ago - Pushed: over 2 years ago - Stars: 11 - Forks: 2

ernestoregue/Arqui

Prácticas (VHDL)

Language: VHDL - Size: 1.12 MB - Last synced: 8 months ago - Pushed: about 3 years ago - Stars: 0 - Forks: 3

OVGN/OpenHBMC

Open-source high performance AXI4-based HyperRAM memory controller

Language: Verilog - Size: 3.57 MB - Last synced: 8 months ago - Pushed: over 1 year ago - Stars: 40 - Forks: 8

DominikCaban/de1_project_sinus

project for DE1 team assignment (D. Caban, I. Dovicak, M. Kováč, L. Kudrna)

Language: VHDL - Size: 69.1 MB - Last synced: 8 months ago - Pushed: about 2 years ago - Stars: 0 - Forks: 4

R4sp1/digital-electronics-1

Language: Tcl - Size: 2.78 MB - Last synced: 8 months ago - Pushed: 8 months ago - Stars: 0 - Forks: 1

theashix/8-bit_multiplier

8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA

Language: SystemVerilog - Size: 20.5 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

Chrisdeleon91/Xilinx-Artix-7-PCIe-Project

Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.

Language: VHDL - Size: 90.8 KB - Last synced: 9 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

gonzafernan/advanced-digital-design

Resolución de laboratorios y guías prácticas asignadas en el curso de Diseño Digital Avanzado 2022.

Language: Jupyter Notebook - Size: 4.04 MB - Last synced: 9 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

dubicube/minitel2.0

Building a modern computing unit out of an old minitel for domotic applications

Language: VHDL - Size: 4.94 MB - Last synced: 9 months ago - Pushed: over 2 years ago - Stars: 4 - Forks: 1

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced: 8 months ago - Pushed: almost 4 years ago - Stars: 29 - Forks: 7

SimoneDeidier/RL-PROJECT-2023

Final project of Logical Networks course - Politecnico di Milano

Language: VHDL - Size: 4.73 MB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 2 - Forks: 0

muxinyu1/buzzer-demo

蜂鸣器demo

Language: Verilog - Size: 39.1 KB - Last synced: 9 months ago - Pushed: 9 months ago - Stars: 0 - Forks: 0

qzxtu/Digital-Logic

Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository

Language: Tcl - Size: 2.01 MB - Last synced: 3 months ago - Pushed: 3 months ago - Stars: 0 - Forks: 1

Reconfigurable-Computing-CalPoly-Pomona/Reconfigurable-BLAST-N

The Blastn (Basic Local Alignment Search Tool for Nucleotides) algorithm with Smith-Waterman scoring implemented for FPGAs

Language: C - Size: 21.4 MB - Last synced: 7 months ago - Pushed: over 4 years ago - Stars: 7 - Forks: 0

Freed-Wu/xilinx-language-server

language server and vim plugin for xilinx vivado and vitis

Language: Vim Script - Size: 1.08 MB - Last synced: 3 days ago - Pushed: 3 days ago - Stars: 0 - Forks: 0

ferrispnugraha/0010-and-100-Sequence-Detector

Mealy Machine with VHDL

Language: VHDL - Size: 765 KB - Last synced: 9 months ago - Pushed: over 3 years ago - Stars: 0 - Forks: 0

z4chh/FPGA_Slot_Machine

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.

Language: SystemVerilog - Size: 12.7 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

gubbriaco/FPGA-VHDL-filtering-circuit-grayscale-images

A project that involves the hardware design (VHDL) of a circuit on FPGA that performs the filtering of an image through an isotropic filter. The circuit is also tested and validated (both from the point of view of the error and from the point of view of the quality of the filtering) through procedures described in MATLAB.

Language: C - Size: 76.8 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

michealcarac/SeniorCapstone

A Hardware-based Keylogging User Authentication System using a Zybo Z7 or Raspberry Pi

Language: VHDL - Size: 539 MB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 2 - Forks: 0

KyleParkJong/Memory-Based-FFT-Accelerator-Controller

Konkuk Univ. 3rd grade, Term-project from Embedded Computing class

Language: C - Size: 12 MB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 1 - Forks: 0

ynarter/EE102

Labs and project for the EE102 Introduction to Digital Circuit Design course.

Language: HTML - Size: 11.8 MB - Last synced: 10 months ago - Pushed: over 1 year ago - Stars: 0 - Forks: 0

Domipheus/ArtyS7-RPU-SoC

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

Language: VHDL - Size: 18.8 MB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 33 - Forks: 6

Abhishek0706/Han-Carlson-Adder

code for printing verilog code of han carlson adder for n bits in python as well as java both.

Language: C - Size: 95.7 KB - Last synced: 10 months ago - Pushed: about 5 years ago - Stars: 6 - Forks: 3

the-snowwhite/mksocfpga3

For finalizing experimental development work on the mksocfpga_hm3 repo back into machinekit

Language: SystemVerilog - Size: 20.5 KB - Last synced: 10 months ago - Pushed: over 6 years ago - Stars: 0 - Forks: 0

Tosainu/ultra96-fractal

Hardware accelerated Julia set explorer running on Ultra96

Language: C++ - Size: 3.57 MB - Last synced: 10 months ago - Pushed: about 2 years ago - Stars: 11 - Forks: 1

nxbyte/ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU

Language: Verilog - Size: 3.96 MB - Last synced: 10 months ago - Pushed: over 5 years ago - Stars: 82 - Forks: 28

Mazan-ka/ps2_mouse_interface

Change the color of square on display via vga with mouse PS2 protocol

Language: Verilog - Size: 9.77 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 0 - Forks: 0

rajivaPavan/Nanoprocessor-Design-Project

This repository contains the VHDL files for a Nanoprocessor Design

Language: VHDL - Size: 1.49 MB - Last synced: 10 months ago - Pushed: 12 months ago - Stars: 1 - Forks: 0

cteqeu/VHDL

Repo for Digitale Systemen - VHDL

Language: VHDL - Size: 65.5 MB - Last synced: 10 months ago - Pushed: about 1 year ago - Stars: 6 - Forks: 6

cteqeu/PynqZ2

Size: 1.95 KB - Last synced: 10 months ago - Pushed: over 3 years ago - Stars: 1 - Forks: 0

MatteoFasulo/Versal-C-Code

Evaluation of timing performance of deep neural networks workloads accelerated on Versal AI Engine in presence of contention on shared resources, mainly caused by ARM Cortex A72 dual-core microprocessor.

Language: Jupyter Notebook - Size: 4.43 MB - Last synced: 10 months ago - Pushed: 12 months ago - Stars: 0 - Forks: 0

perehinik/Logic_Analyzer_FPGA_Config

Vivado project for Xilinx Artix FPGA, used in logic analyzer

Language: VHDL - Size: 21.5 MB - Last synced: 10 months ago - Pushed: almost 3 years ago - Stars: 8 - Forks: 2

suoglu/Queue-Management-System

Simple queue management system

Language: Verilog - Size: 43.9 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 3 - Forks: 2

suoglu/Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

Language: Verilog - Size: 140 KB - Last synced: 10 months ago - Pushed: 10 months ago - Stars: 42 - Forks: 11