trungnob/MicroBlaze

Language: LabVIEW - Size: 30.9 MB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 0

olivier-le-sage/camera-filters

Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.

Language: VHDL - Size: 64.4 MB - Last synced at: almost 2 years ago - Pushed at: about 5 years ago - Stars: 21 - Forks: 15

vinayak1998/Multiplier-Design

Language: VHDL - Size: 1.16 MB - Last synced at: almost 2 years ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 0

vinayak1998/Reflex-Tester

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

Language: VHDL - Size: 1.02 MB - Last synced at: almost 2 years ago - Pushed at: almost 8 years ago - Stars: 4 - Forks: 0

vinayak1998/7-segment-display-fpga

Design and implement a Seven Segment Display available on the BASYS3 board (FPGA) in VHDL

Language: VHDL - Size: 455 KB - Last synced at: almost 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 0

Abhishek-Sharma94/Single-cycle-MIPS-processor

This project is about simulating the single cycle MIPS processor using Matlab and Xilinx tools. Separate files are created for each component in the MIPS processor.

Language: MATLAB - Size: 54.7 KB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

mattuna15/merlin

Learn how to create your own 32-bit system from scratch.

Language: Assembly - Size: 19 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 11 - Forks: 2

SamsonAdem/HW_SW_Co_Design_FPGA

Hardware accelerator for Image processing in FPGA

Language: C++ - Size: 41.7 MB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Torusaynim/Mirea-Hardware-Software-Development

📋 List of practical and laboratory works from Hardware&Software Development subject from university

Language: VHDL - Size: 15.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

simoneruffini/NORM

Framework for emulation of non volatile memory using off-the-shelf FPGAs

Language: VHDL - Size: 27.2 MB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 7 - Forks: 1

ChienKaiMa/2021_ACA_HLS_team05

High level synthesis projects and practices

Language: C++ - Size: 54.7 KB - Last synced at: 10 days ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

mm-mehran79/networkPacket_stuffOrData

the module is also known as sigma delta

Language: SystemVerilog - Size: 3.04 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

UofT-HPRC/galapagos_aes

AES example using Galapagos Framework

Language: VHDL - Size: 12.6 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

tum-bgd/dwc

Language: Python - Size: 16.6 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

davidParraga/FPGA_UART_Module

Design for FPGA of a Universal Asynchronous Receiver Transmitter.

Language: C - Size: 2.41 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

oliviercotte/Digilent-Atlys-Boot-Linux-Image

Digilent Atlys Board Linux Flash Image

Size: 9.34 MB - Last synced at: about 2 years ago - Pushed at: over 7 years ago - Stars: 2 - Forks: 0

DiegoRosales/Zybo_Sampler

Audio Sampler for Zybo

Language: C - Size: 43.1 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 1

DylanVanAssche/digitale-synthese

DSSS Wireless transmit-receive system in VHDL

Language: VHDL - Size: 14.6 MB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 7 - Forks: 2

wurmmi/fm-radio

Master thesis project - Comparing a FM Radio implementation in VHDL versus high-level synthesis (HLS).

Language: VHDL - Size: 347 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

abrazisaeid/GPIO_Zynq7020

It is a simplified GPIO interrupt example for Xilinx ZYNQ FPGA.

Language: HTML - Size: 5.23 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 1

JakubKajzer/Trugbild

An FPGA working in serial with HDMI, for some real live video modifications

Size: 9.84 MB - Last synced at: about 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

AnyDSL/anyhls

High-Level Synthesis with Partial Evaluation

Language: CMake - Size: 81.1 KB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 11 - Forks: 1

neeraj1397/Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

Language: Verilog - Size: 653 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 2

sailordiary/computer-systems-ucas

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Language: Verilog - Size: 52.4 MB - Last synced at: about 2 years ago - Pushed at: over 8 years ago - Stars: 27 - Forks: 8

hex-five/multizone-fpga Fork of sifive/freedom

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.

Language: Scala - Size: 212 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 24 - Forks: 5

ctsiaousis/mipsMultiCycleProcessor 📦

A VHDL implementation of a MIPS processor with multicycle instruction fetching

Language: C - Size: 1.36 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 0

charkster/cmod_a7_pattern_generator_v1

Language: SystemVerilog - Size: 157 KB - Last synced at: 2 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

ilyajob05/verilog_modules

verilog modules

Language: Verilog - Size: 27.3 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 8 - Forks: 2

WualFabre/FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

Language: Verilog - Size: 5.35 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 1

stevenbell/csirx

Open-source CSI-2 receiver for Xilinx UltraScale parts

Language: Verilog - Size: 11.6 MB - Last synced at: about 2 years ago - Pushed at: about 6 years ago - Stars: 32 - Forks: 13

bsc-pm-ompss-at-fpga/ompss-at-fpga-releases

Meta-repository for OmpSs@FPGA releases

Language: Dockerfile - Size: 186 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

Yourigh/Rotary-encoder-VHDL-design

VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.

Language: VHDL - Size: 25.4 KB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 10 - Forks: 2

Ryuzaki101/Programmable-logic-components

Xilinix VHDL Projects

Language: C - Size: 3.49 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0

amineremache/Pong_VHDL_FPGA

A VHDL Project using ISE 14.7, developed on a Xilinx Spartan 6

Language: HTML - Size: 3.14 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

IzyaSoft/EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

Language: Verilog - Size: 315 KB - Last synced at: 6 months ago - Pushed at: over 8 years ago - Stars: 6 - Forks: 0

Gabriele-bot/ALVEO-PYNQ_ML

Neural network inferences on Alveo cards with hls4ml framework

Language: Ada - Size: 786 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1

IanArko/MIPS_CPU

This is a functioning MIPS CPU designed in Verilog to run an an xilinx fpga.

Language: Verilog - Size: 3.76 MB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

pontazaricardo/Verilog_Calculator_Matrix_Multiplication

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Language: Verilog - Size: 3.73 MB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 34 - Forks: 8

DOUDIU/Multiplication-of-single-precision-flooat-matrix-based-on-FPGA

The achievement of performing matrix multiplication on a single-precision floating-point matrix, which adheres to the IEEE 754 standard, is dependent on Xilinx FPGA.

Language: Verilog - Size: 27.3 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

mwil/wifire

FPGA and firmware images for the USRP2 to operate as a Wireless Firewall (WiFire)

Language: C++ - Size: 4.36 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 5 - Forks: 2

kurtasli/Voice-Synthesizer

Voice Synthesizer

Language: VHDL - Size: 5.81 MB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

solomspd/RISC-V-CPU

RISC-V 5-stage pipeline RV32I implementation with forwarding in verilog with drivers to work on xilinx nexus a7 FPGA boards

Language: Verilog - Size: 1.15 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

KarenOk/SAP-1-Computer

Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.

Language: VHDL - Size: 2.25 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 14 - Forks: 8

kuoyaoming93/sem-ip_pynq

SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2

Language: Tcl - Size: 17.8 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 1

diogofferreira/fpga-miner

:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:

Language: VHDL - Size: 344 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 32 - Forks: 23

amin-mamandi/Xilinx-Vitis-AI

The Flow to Deploy your Custom Deep Learning Models on Ultra96V2.

Language: Python - Size: 3.14 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Accelize/nimbix_drm_demo 📦

This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.

Language: C++ - Size: 28.6 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 0

Jpfonseca/Reconfigurable_Computing 📦

Reconfigurable_Computing course

Language: VHDL - Size: 141 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 3 - Forks: 0

zpekic/Sys0800

VHDL implementation of vintage TMS0800 calculator chip

Language: VHDL - Size: 7.99 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 3

mcagriaksoy/VHDL-FPGA-LAB_PROJECTS

My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)

Language: VHDL - Size: 575 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 2

hossein1387/ZYBO

This repository contains my Linux builds and projects for ZYBO Zynq dev board

Language: Tcl - Size: 14.6 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 6 - Forks: 5

andrsmllr/spartan3e_starter_devbrd

Play and learn with the Digilent Spartan3E-Starter board featuring a Xilinx Spartan-3E XC3S500E FPGA and various peripherals.

Size: 2.93 KB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 1

theshadowx/keyboard-ip

PS/2 Keyboard IP written in VHDL for Xilinx FPGA

Language: VHDL - Size: 174 KB - Last synced at: over 2 years ago - Pushed at: about 10 years ago - Stars: 14 - Forks: 2

rgalland/Bin2COEConverter

Small C program to convert a bin file to COE; a format used by Xilinx to load memory contents.

Language: C - Size: 27.3 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

ujwalnk/VerilogBasics

Verilog Code for basic Operations

Language: Verilog - Size: 25.4 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

cescalara/zynq_ip_hls

Custom IP for the Mini-EUSO PDM-DP Zynq system

Language: C++ - Size: 7.81 MB - Last synced at: 22 days ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

cescalara/l2trigger_hw_testbench

Hardware testbench project for the Mini-EUSO L2 trigger (HLS implementation)

Language: VHDL - Size: 141 MB - Last synced at: 22 days ago - Pushed at: about 6 years ago - Stars: 1 - Forks: 0

teoyuqi/Running-Vitis-AI-on-Avnet-UltraZed-EG-IOCC

A guide to implementing deep-learning applications using the Xilinx Vitis-AI tech stack

Language: Python - Size: 336 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1

devdotnetorg/Hastlayer

.NET for FPGAs with Hastlayer

Size: 14.6 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

manish257/Displaying-on-Seven-Segment-of-FPGA-using-Verilog

Language: HTML - Size: 438 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

Wissance/2DImageProcessing

2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)

Language: VHDL - Size: 36.9 MB - Last synced at: about 1 month ago - Pushed at: about 8 years ago - Stars: 11 - Forks: 6

ChamanAgrawal/CS220

This repository contains lab assignments done in the course CS220: Computer Organization at IIT Kanpur

Language: HTML - Size: 4.42 MB - Last synced at: over 2 years ago - Pushed at: about 6 years ago - Stars: 8 - Forks: 0

lild4d4/usm_microcontroller_v1

Undergraduate level RISC-V microcontroller

Language: SystemVerilog - Size: 201 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

MaharshSuryawala/Microprocessor-Without-Interlocked-Pipeline-Stages-MIPS

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.

Language: Verilog - Size: 5.53 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 1

nickschiffer/cla_adder_7seg

4bit_CLA_Adder_7seg in Xilinx Vivado Verilog

Language: HTML - Size: 601 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

CustomRobotics/V-AIye

Adaptive Computer Challenge Project @ Hackster.IO

Language: C - Size: 139 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

oaxelou/FPGAs

Hardware - Verilog

Language: Verilog - Size: 6.14 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

SMATEO49/Project-of-Painting-Robot

My own project in VHDL using ISE Xilinx and FPGA component xc3s200-5ft256

Language: C - Size: 1.28 MB - Last synced at: 7 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

ilyajob05/verilog_SPI

SPI module for Nexys 4 Artix-7 FPGA Trainer Board

Language: Verilog - Size: 38.1 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

SymbiFlow/prjuray-tools

Language: C++ - Size: 1.74 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 2

ranjith-dhananjaya/IRNSS-Standard-Satellite-Signal-Generator

This repository contains the files used in the design and simulation of Indian Regional Navigation Satellite System (IRNSS) Signal Generator

Size: 225 KB - Last synced at: about 2 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

hypercurious/fpga-projects

University projects on FPGA including the implementation of a digital clock on a seven segment and a calculator getting inputs from a ps2 keyboard and showing the result on the seven segment

Language: Verilog - Size: 1.3 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 0

majorlin/xloader

Xilinx FPGA loader

Language: Verilog - Size: 330 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 1

NishadSaraf/Colorwheel-Implementation-On-FPGA

Displays colorwheel on OLED display in HSV scale on Xilinx Nexys 4DDR FPGA

Language: C - Size: 540 KB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 0

satvik-tha-god/tic_tac_toe

Implemented FPGA Tic-Tac-Toe

Language: HTML - Size: 167 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

PZHengwf/post_iap_fpga

基于Xilinx Virtex-5在线更新FPGA外部FLASH，修改FPGA配置文件，完成IAP在线更新；

Size: 857 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

MossbauerLab/MessbauerTestEnvironment

FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified

Language: Verilog - Size: 2.84 MB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 1

billalkuet07/Reconfigurable-Encryption-System-Encrypt-Digital-Data

This paper presents a reconfigurable system that can encrypt digital data. The system provides the option of choosing one of familiar encryption methods DES, 3 DES and AES to the user.

Size: 1.9 MB - Last synced at: over 2 years ago - Pushed at: almost 8 years ago - Stars: 2 - Forks: 2

splAcharya/LowPassFilterFPGA

Designed and Implemented a low pass filter in Nexys 4 FPGA

Language: VHDL - Size: 39.8 MB - Last synced at: 11 months ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

AlmuHS/Binary_to_BCD_Display

Project to show in a BCD display a value set in binary

Language: VHDL - Size: 30.3 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 0

zdzislaw-s/oled-driver-demo

OLED driver demo running on ZedBoard

Language: PHP - Size: 22.6 MB - Last synced at: 4 months ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 3

haoyang-graphics/cyber-melody-2

Cyber Melody 2 on MIPS!

Language: Verilog - Size: 3.64 MB - Last synced at: 6 months ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

ckevar/IIR-Filter

IIR Filter for audio application

Language: VHDL - Size: 10.7 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 4

lucarinelli/computer_architecture_project

Our project material for the Computer Architecture course for Computer Engineering students at Politecnico di Torino (Polytechnic University of Turin)

Language: VHDL - Size: 97.1 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 4 - Forks: 0

kirk-loeten/MESA-Stepcraft-BIT-Files

compiled bit-file for 6i25 with stepcraft

Language: VHDL - Size: 468 KB - Last synced at: 13 days ago - Pushed at: almost 6 years ago - Stars: 1 - Forks: 0

naashonomics/Xilinx_ML_suite

Language: HTML - Size: 1.03 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 1 - Forks: 0

TurtleTaco/Janus-C-Plus-Plus

Janus Algorithm in C++ version without FPGA acceleration.

Language: Ada - Size: 10.2 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

TurtleTaco/Janus-Simulation

Janus astrophysics Simulator implemented on ZU19EG Ultrascale+

Language: LLVM - Size: 187 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

NishadSaraf/RTOS-Driven-Closed-Loop-Control-System

PID control on Xilinx Nexys 4DDR FPGA board using XilKernel

Language: C - Size: 1.02 MB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 0

PetarZecevic/CatchTheFlowers Fork of stefan9x/lprs2-TowerDefence

Video game made for E2LP, FPGA board, as a project for course Logic Design of Computer Systems 2

Language: C - Size: 20.6 MB - Last synced at: 5 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1

monsij/eC-Circuits

Shaped by Kiel c51

Language: C - Size: 41 KB - Last synced at: 6 months ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

Sumegh-git/Xilinx-Innovation-Challenge

Team reverse_biased

Language: Python - Size: 15.1 MB - Last synced at: about 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 1

mcagriaksoy/DegreeAdjustableRadar

Zynq ZedBoard SoC Lecture Final Project, degree adjustable ultrasonic sensor application

Language: VHDL - Size: 219 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 0

JoseCVieira/JacobiMethod-HwSw-Architecture

Implementation of Jacobi method in a co-processing architecture Hw/Sw using FPGA (Field Programmable Gate Array) ZYBO Zynq-7000 Development Board for Co-Project Hw/Sw course.

Language: VHDL - Size: 196 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 2 - Forks: 1

JiriS97/BLOS-Projects

Working projects from BLOS lessons on Brno University of Technology

Language: VHDL - Size: 5.55 MB - Last synced at: 10 months ago - Pushed at: almost 8 years ago - Stars: 1 - Forks: 0

NishadSaraf/Bare-Metal-Closed-Loop-Speed-Control-System

Bare metal (without embedded OS) DC motor speed control system

Language: Verilog - Size: 763 KB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 0

ismenc/fpga-vga-driver-game

This is 'space invaders' game and VGA driver builded on Xilinx ISE + Spartan 3

Language: VHDL - Size: 1.75 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0