GitHub topics: verilator
Risto97/systemc_uvm_verilator 📦
Language: C++ - Size: 1.42 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 11 - Forks: 0
streetdogg/riscv-cpu-rtl
Implements a RISC-V CPU (rv32i) with base ISA
Language: C++ - Size: 17.6 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1
npatsiatzis/recirculation_mux
Language: Python - Size: 10.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/fifo_asynchronous
Language: Python - Size: 7.09 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/fir
Language: Python - Size: 69.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/moving_average
Language: Python - Size: 53.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/fizzbuzz
Language: Python - Size: 10.8 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/uart
Language: VHDL - Size: 12.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/fifo_synchronous
Language: C++ - Size: 77.1 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
fredrequin/verilator_helpers
C++ objects to help verilator simulations
Language: C - Size: 149 KB - Last synced at: about 1 year ago - Pushed at: over 2 years ago - Stars: 2 - Forks: 0
ShaheerSajid/RISCV
32-bit soft RISCV processor for FPGA applications
Language: C++ - Size: 13.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 8 - Forks: 0
npatsiatzis/simple_adder
Language: Python - Size: 17.7 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/barrel_shifter
Language: C++ - Size: 7.39 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
geekboi777/RISC-V_CPU_Core
This repository contains the working developer code for a RISC-V_CPU_Core made using TL-Verilog , Makerchip IDE, Sandpiper and Verilator.
Language: Verilog - Size: 37.1 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0
npatsiatzis/cdc_handshake
Language: Python - Size: 7.14 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
npatsiatzis/VGA
Language: SystemVerilog - Size: 4.46 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0
jsren/verilator-reflect
Fork of Verilator adding ability to iterate over references to internal signals by name.
Language: C++ - Size: 4.28 MB - Last synced at: almost 2 years ago - Pushed at: about 8 years ago - Stars: 0 - Forks: 0
stephenry/qs
A hardware implementation of the Quicksort algorithm.
Language: SystemVerilog - Size: 446 KB - Last synced at: almost 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 1
kkiningh/rules_verilator_old 📦
A fork of Verilator that includes Bazel build rules
Language: C++ - Size: 6.6 MB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 3 - Forks: 0
sfu-arch/muir-sim
muIR C++ Simulator
Language: C++ - Size: 434 MB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 3
vmunoz82/eda_tools
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
Language: Dockerfile - Size: 17.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 24 - Forks: 4
Rain92/vga_interface
Language: SystemVerilog - Size: 1.65 MB - Last synced at: about 2 years ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 2
dbhi/vboard
Virtual development board for HDL design
Language: VHDL - Size: 383 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 33 - Forks: 5
FDUCSLG/ICS-2021Spring-FDU
Introduction to Computer Systems (II), Spring 2021
Language: C++ - Size: 24.8 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 30 - Forks: 17
ZipCPU/zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Language: Verilog - Size: 3.03 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 36 - Forks: 5
nju-mips/noop-lo
A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
Language: Verilog - Size: 19.4 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 19 - Forks: 5
wataru030-XIAOHEI/My-RISCV64-CORE-writing
一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
Language: C++ - Size: 1.2 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 13 - Forks: 3
ruibailin/FtoCDT
C/C++ projects which are friendly to Eclipse CDT
Size: 82.7 MB - Last synced at: about 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0
ndyashas/Salaga-RV
Simple RISC-V CPUs running a baremental ray-tracer program.
Language: Verilog - Size: 884 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
scarv/scarv-cpu
SCARV: a side-channel hardened RISC-V platform
Language: Verilog - Size: 1.37 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 18 - Forks: 6
gergoerdi/clash-bounce-bench
Benchmark for various methods of simulating Clash
Language: Haskell - Size: 69.3 KB - Last synced at: 3 months ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0
ssayin/nandgame-sv
Experimental
Language: SystemVerilog - Size: 5.54 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
ZipCPU/dbgbus
A collection of debugging busses developed and presented at zipcpu.com
Language: Verilog - Size: 324 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 23 - Forks: 3
xThaid/fpga-lb
A toy L4 load balancer running on FPGA
Language: C - Size: 832 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 10 - Forks: 0
weisrc/web-verilog-poc
Running verilog on hardware, desktop and the web
Language: C++ - Size: 167 KB - Last synced at: 2 months ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 0
verilator/uvm Fork of chipsalliance/uvm-verilator
Universal Verification Methodology (UVM) base libraries, with edits for Verilator
Size: 0 Bytes - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 18 - Forks: 8
ECE320/riscv-tester
Tests your ECE 320 Single Cycle RISC-V Processor: Up to PD5
Language: Python - Size: 101 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 0
LaloHao/verilator_test
Basic functionality for simulating verilog crafted circuits using verilator
Language: C++ - Size: 2.93 KB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 1
rodrigomelo9/verifying-foss-hdl-synthesizers
a project to check the FOSS synthesizers against vendors EDA tools
Language: Makefile - Size: 81.1 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 12 - Forks: 2
Lampro-Mellon/Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
Language: Scala - Size: 155 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 23 - Forks: 8
supleed2/dmpvl Fork of DaveMcEwan/dmpvl
Dave McEwan's Personal Verilog Library
Language: SystemVerilog - Size: 164 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0
esromneb/verilator-project-template
Template Verilator project for beginners
Language: C++ - Size: 59.6 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 10 - Forks: 1
coldnew/nand2tetris
My notes and impement on Nand2Tetris courses
Language: Assembly - Size: 9.37 MB - Last synced at: 3 months ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
SDZZGNDRC/XPU-diff
The diff-test environment of the XPU project.
Language: Assembly - Size: 6.38 MB - Last synced at: about 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0
jeudine/Mersenne-twister-hardware
A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which uses Verilator were created in order to verify the correctness and to measure performance of the hardware module.
Language: C++ - Size: 59.6 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 0
ZipCPU/s6soc
CMod-S6 SoC
Language: Verilog - Size: 2.8 MB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 33 - Forks: 5
SymbiFlow/XilinxUnisimLibrary Fork of Xilinx/XilinxUnisimLibrary
Apache 2.0 licensed copy of the Xilinx Unisim library.
Language: Verilog - Size: 1.9 MB - Last synced at: over 1 year ago - Pushed at: almost 5 years ago - Stars: 8 - Forks: 1
nju-mips/workbench
Workbench of nju-mips, this repo implements a ready-to-work framework for CPU development. It uses differential testing to help find implementation bugs.
Language: Verilog - Size: 345 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 3
Ray-Eldath/althas
A header-only C++ library that provides unit test facilities for Verilator which makes your testing procedure much easier.
Language: C++ - Size: 23.4 KB - Last synced at: about 6 hours ago - Pushed at: almost 5 years ago - Stars: 6 - Forks: 0
DuinOS/AprendaFPGA
Algumas anotações de quem está aprendendo a sintetizar seu próprio microcontrolador em FPGA.
Size: 23.4 KB - Last synced at: 8 days ago - Pushed at: about 4 years ago - Stars: 2 - Forks: 0
Aj0SK/verilog
Simple CPU design based on Nand game in Verilog
Language: C++ - Size: 86.9 KB - Last synced at: 27 days ago - Pushed at: almost 5 years ago - Stars: 0 - Forks: 1
euripedesrocha/tbpp
A simple test library for verilator
Language: C++ - Size: 128 KB - Last synced at: 3 months ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0
rjb32/verilog-simple
Example of a simple Verilog module with a C++ test bench using Verilator.
Language: C++ - Size: 3.91 KB - Last synced at: 3 months ago - Pushed at: about 6 years ago - Stars: 0 - Forks: 0
hongping/verilator_helloworld
Hello World example for using Verilator
Language: C++ - Size: 0 Bytes - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
tocisz/verilog-cellular-automaton
My first Verilog
Language: Verilog - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0
nsailor/Feather
A single cycle processor implementing a subset of the ARMv7 ISA.
Language: SystemVerilog - Size: 147 KB - Last synced at: 2 months ago - Pushed at: over 6 years ago - Stars: 1 - Forks: 1
msvisser/mMIPS-Verilator
Verilator testbench for the mMIPS processor
Language: C++ - Size: 18.6 KB - Last synced at: almost 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0
