Bengal1/MIPS-32-bits-Micro-Processor

Reduced MIPS 32-bit Processor

Language: Verilog - Size: 208 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

JN513/estudos_verilog

Exemplos feito em verilog para estudos

Language: Verilog - Size: 10.6 MB - Last synced at: 8 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

mshr-h/motion_estimation_processor_fullsearch

Fullsearch based Motion Estimation Processor written in Verilog-HDL

Language: Verilog - Size: 1.7 MB - Last synced at: about 1 month ago - Pushed at: over 8 years ago - Stars: 11 - Forks: 3

mohamedtareq24/ASICs_Design_Diploma

RTL to GDSII flow of a low Power configurable multi clock digital system

Language: Verilog - Size: 31.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

lolooppo/coa_assignments

this repo contains 2 assignments during my computer organization and architecture course.

Language: VHDL - Size: 5.86 KB - Last synced at: 5 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Runhane/Space-Invader

this project is realized by DE2-115、OpenMV、HC-05

Language: Verilog - Size: 38.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

dhwanish-3/Verilog-Programming-Logic-Design-Lab

Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator

Language: Verilog - Size: 28.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Crazy2code15/Verilog__SV_VHDL

.v , .vhdl & .sv Lab

Language: Verilog - Size: 3.18 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

aamodbk/iiitb_aclock

Design and Implementation of Alarm clock through PD flow

Language: Verilog - Size: 2.95 MB - Last synced at: over 1 year ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

sarthak268/Embedded_Logic_and_Design

This repository contains all labs done as a part of the Embedded Logic and Design course.

Size: 14.7 MB - Last synced at: over 1 year ago - Pushed at: over 7 years ago - Stars: 21 - Forks: 2

deepan19/Hardware-Accelerated-Video-Compression-using-DCT

Individual Contributions to my team's CPEN 391 final project. I developed the video frame capture system for the D8M, created Avalon slaves for hardware-software interfacing and the DCT hardware accelerator

Language: Verilog - Size: 951 KB - Last synced at: almost 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 1

cvonk/FPGA_SPI

Connecting FPGA and Arduino using SPI.

Language: Verilog - Size: 2.52 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 20 - Forks: 3

TAKE72K/HDLPractice

Repo of my HDL exercises

Language: Verilog - Size: 110 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

mseminatore/fpgacoding

Source code companion to the fpgacoding.com blog

Size: 72.3 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 5 - Forks: 0

arlotfi79/MIPS-Processor 📦

A 32-bit MIPS Processor Implementation in Verilog HDL

Language: Verilog - Size: 24.4 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

nyLiao/Whac-A-Mole-FPGA 📦

A project by Verilog HDL to play the whac-a-mole game on BASYS 2 FPGA board.

Language: Verilog - Size: 320 KB - Last synced at: almost 2 years ago - Pushed at: about 6 years ago - Stars: 2 - Forks: 0

SatyenderYadav/verilog-code

These are verilog codes for the different ICs

Language: Verilog - Size: 596 KB - Last synced at: almost 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 1

JochiSt/pyVHDLinstTemplate

create a VHDL instantiation template from Verilog source

Language: Python - Size: 21.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

JN513/riscv-isa-ci 📦

CI/CD for RISC-V Cores

Language: Verilog - Size: 1.32 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 4 - Forks: 0

164adityakumar/Image_Encryption_I-CHIP

This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm

Language: Verilog - Size: 9.38 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

KatelynLam97/-Digital-Systems-Project-Microwave

Size: 84 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Emreozgun/Single-cycle-MIPS

Size: 233 KB - Last synced at: almost 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

vicharak-in/vaaman-ahb-verilog

Verilog AHB Bus implementation for VAAMAN

Language: Verilog - Size: 25.4 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Sudeep-Dhurua/verilog-to-gate-level-synthesis

This Project consist of a first level synthesizer. It will take a Hardware-Description written in Verilog standard (or ****.v) file and convert it into gate level netlist.

Size: 0 Bytes - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

ngiambla/qvmi

Quick Verilog Module Isolator - Isolates a design for testing.

Language: Verilog - Size: 233 KB - Last synced at: almost 2 years ago - Pushed at: almost 7 years ago - Stars: 3 - Forks: 0

gonzafernan/cese-mys-zynq7

Microarquitecturas y Softcores - CESE - FIUBA

Language: Verilog - Size: 1.25 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

mukullokhande99/fifo_hardware_fpga

FIFO implemented on FPGA Spartan 6

Language: Rich Text Format - Size: 21.4 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 1

DHEEPAK29/Verilog_implementation_of_Vending_Machine

A sequence detector is a sequential state machine. In a Moore machine, output depends only on the present state and not dependent on the input (x). Hence in the diagram, the output is written with the states. In a mealy machine, output depends both on the present state and on the input (x). The vending machine takes coins as inputs in virtually any sequence and delivers products when Required amount is deposited and provides back the modification that is noticeable entered quantity is more than the price of product. The proposed algorithm is implemented in Verilog HDL and simulated Xilinx ISE simulator.

Size: 5.86 KB - Last synced at: almost 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Nurhak/VivadoTutorial

Size: 18.9 MB - Last synced at: almost 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

sjkeller/smart-sensors-project

Verilog implementations of different simple tasks

Language: Verilog - Size: 411 KB - Last synced at: almost 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

ArjunBasandrai/verilog-reference

Verilog programs for VIT Vellore Digital System Design Lab course (2023)

Language: Verilog - Size: 17.6 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Efesasa0/32-bit-cpu

In CMPSC 331 2019, I implemented a design of 32-bit-pipelined cpu design.

Language: Verilog - Size: 793 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Dhruv0Upadhyay/100_Days_of_RTL

100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog

Language: Verilog - Size: 1.05 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 3 - Forks: 0

nekoday/ElecDesign-University-2021 📦

Adjustable sinusoidal signal generator based on FPGA

Language: Verilog - Size: 26.4 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

gugolple/PicoRV32_BasicProject

Simplest project of a soft-cpu (picorv32) with a complete software environment.

Language: Shell - Size: 1.03 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

manikajain11/Traffic-Signal-Controller

Designing and Modelling of an Intelligent Traffic Signal Controller using FSM in Verilog HDL

Language: Verilog - Size: 1.14 MB - Last synced at: almost 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

otabek7/Datapath_Components_2

Language: Verilog - Size: 218 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

pratikbhuran/Voting_Machine

Voting machine implemented in verilog

Language: Verilog - Size: 146 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 5 - Forks: 1

yusatll/CSE-331-Computer-Organization

Computer Organization

Language: Assembly - Size: 1.99 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

otabek7/Intro_to_Verilog

Language: Verilog - Size: 442 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Multimedia-Processing/Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Language: Verilog - Size: 181 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 6 - Forks: 2

Shuregg/miet-interfaces

Interfaces of computing systems

Language: SystemVerilog - Size: 4.74 MB - Last synced at: 8 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

muznahsaqiib/3-bit-adder-

Size: 1.95 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

DanielGunna/VeitchKarnaugh-Verilog-Examples

Some examples of Veitch-Karnaugh maps solved using verilog language developed as coursework of Architecture and Computer Organization I- @Puc Minas

Language: VHDL - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: almost 8 years ago - Stars: 3 - Forks: 0

AbdullahAnsarii/BandPassFilter

FIR band-pass filter using Verilog HDL.

Language: Verilog - Size: 1.6 MB - Last synced at: about 2 years ago - Pushed at: about 5 years ago - Stars: 7 - Forks: 3

Saadia-Hassan/Types-of-Verification-Using-SRAM

This repo contains golden vector and randomization testbenches for SRAM module.

Language: Verilog - Size: 7.81 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 2

Saadia-Hassan/Real-Time-Clock-Module

A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.

Language: Verilog - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Saadia-Hassan/Traffic-Light-Controller-Using-FSM

An automatic traffic light controller is designed and simulated using the concept of Finite State Machine in ModelSim.

Language: Verilog - Size: 2.93 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

Saadia-Hassan/8x8Multiplier-Using-Vedic-Mathematics

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

Language: Verilog - Size: 4.88 KB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 5 - Forks: 2

TILhub/SystemC-Introduction

SystemC is a set of C++ classes and macros which provide an event-driven simulation interface (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax.

Language: C++ - Size: 388 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 4 - Forks: 3

ibrhmkrt/VerilogHDL

VerilogHDL project

Language: Verilog - Size: 74.2 KB - Last synced at: about 2 years ago - Pushed at: about 7 years ago - Stars: 0 - Forks: 0

aula9/Computer-Design-of-Electronic-Circuits-Lectures

Size: 12.2 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

pawan-nirpal-031/ComputerArchitecture-MicroprocessorDesign

Basic Microprocessor Design in HDLs like Verilog.

Language: C++ - Size: 5.66 MB - Last synced at: about 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

Howeng98/FloatingPointAdder

floating point adder

Language: Verilog - Size: 2.5 MB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 2 - Forks: 2

kitune-san/KFMMC_V2

Multi media card access controller written in HDL

Language: Verilog - Size: 168 KB - Last synced at: 6 months ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

cvonk/FPGAmath

Verilog HDL implementations of adders/subtractor, multiplier, divider and square root. As well as HTML simulations.

Language: JavaScript - Size: 67.6 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 3

sumitarohit/Array_Multiplier_project

This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.

Language: Tcl - Size: 179 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

varunram2001/VerliogCodes

This repository contains all the Verilog codes and their testbenches that I have compiled as a part of my academic journey in Electronics and Communication Engineering.

Language: SystemVerilog - Size: 1.26 MB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

Artityagi123456789/Verilog_Course_Report

Digital Design using Verilog

Size: 4.18 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

Arjun-Narula/Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

Language: JavaScript - Size: 2.07 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 29 - Forks: 7

omerbitikcioglu/gtu-homeworks

Language: C - Size: 50.5 MB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

alanmimms/kl10

KL10PV (also called "model B") CPU implemented in SystemVerilog for Xilinx FPGA from MP00301_KL10PV_Jun80 PDFs trying to remain faithful to the original while I learn Verilog

Language: SystemVerilog - Size: 223 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 2 - Forks: 0

MelvinMo/HDL_Course_Archive

This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.

Language: Verilog - Size: 2.21 MB - Last synced at: 19 days ago - Pushed at: about 2 years ago - Stars: 0 - Forks: 0

Gurusatwik/PWM-Generator

This repository focuses on how to design a PWM Generator with variable Duty cycle

Language: Verilog - Size: 67.4 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

einstein07/Vivado-IP-and-Resource-Usage

Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

Language: VHDL - Size: 12.8 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

Shreesh-Kulkarni/Hardware-Modelling-Verilog

All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL

Language: Verilog - Size: 153 KB - Last synced at: almost 2 years ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

Priyanshu-1012/HDLBits-Solutions

verilog practice

Language: Verilog - Size: 178 KB - Last synced at: about 2 years ago - Pushed at: about 2 years ago - Stars: 1 - Forks: 0

EngCake/icarus-verilog

Quick starter project for using Icarus Verilog + Cocotb

Language: Python - Size: 3.91 KB - Last synced at: over 1 year ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

h-kaushik/scalable-cordic

Self-project on describing CORDIC algorithm for calculation of arctan(y/x) using Verilog.

Language: Verilog - Size: 2.93 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

h-kaushik/single-precision-arithmetic

Self-project on describing hardware for complex addition and multiplication based on IEEE-754 single precision arithmetic.

Language: Verilog - Size: 4.88 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

madmaverickminion/Soil-monitoring-bot

This repository contains all the work(till task 5) of Soil Monitoring Bot theme(eYRC-2021-22).

Language: Verilog - Size: 26.7 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

jakemcdermott/docker-yosys

Docker Image for Yosys

Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 1

SvrAdityaReddy/Inter_Device_Communication_Protocols

Verilog Codes of various Inter Device Communication Protocols

Language: SystemVerilog - Size: 377 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 3 - Forks: 1

Mazan-ka/ps2_mouse_interface

Change the color of square on display via vga with mouse PS2 protocol

Language: Verilog - Size: 9.77 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

cgsdfc/mips-pipeline-cpu.verilog

A simple five-stage pipeline MIPS CPU in Verilog.

Language: Assembly - Size: 45.1 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

stineje/prefix_adders

Prefix adder generators for Verilog

Language: Perl - Size: 59.6 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 4

maazm007/100Daysof_RTL

The Repository contains the code of various Digital Circuits

Language: Verilog - Size: 20.6 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 7 - Forks: 1

suoglu/Queue-Management-System

Simple queue management system

Language: Verilog - Size: 43.9 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 3 - Forks: 2

alaattinyilmaz/hardware-description-languages

Coding lab assignments of Hardware Description Languages course in Verilog and VHDL programming languages.

Language: Verilog - Size: 687 KB - Last synced at: over 2 years ago - Pushed at: over 7 years ago - Stars: 1 - Forks: 0

SagarDevAchar/endmodule

Open Source Verilog Modules

Language: Verilog - Size: 52.7 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

nawalmunif/Image-Processing-on-FPGA

An efficient FPGA-based design and implementation of image processing algorithm is presented using verilog hardware description language on Xilinx Vivado.

Size: 36.5 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 0

icglue/stimc

a lightweight Verilog-vpi Wrapper for Stimuli Generation

Language: C - Size: 723 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0

SuchithraM008/HDL-code-for-Y-A-TB-using-only-one-MAC

A^T*B using only one MAC

Language: Verilog - Size: 16.6 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

yilmaz0734/FPGATictactoegame

In this project, we implemented a different kind of a tic tac toe board game that is played on an FPGA board using its push buttons. We used Verilog HDL to code the project and implemented a VGA interface for visualization.

Language: Verilog - Size: 22.8 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

maverick-sp/Project_Vending_Machine_Using_VerilogHDL

This is a project I did during my Digital Design Course

Language: Verilog - Size: 141 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

SantoshSrivatsan24/alu_synthesis

Verilog description of an ALU along with the Cadence Genus tcl script files needed to synthesize it.

Language: Verilog - Size: 473 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 0

jnguyen38/fpga-ml-processor

Used Verilog HDL modules in Quartus Prime Software to simulate a machine learning processor on an FPGA board. UART protocol was used for used input.

Language: Verilog - Size: 5.33 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

saikumargadde2807/HDLBITS_solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

Language: Verilog - Size: 56.6 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Gcerpa01/CompE470

Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023

Language: Verilog - Size: 7.5 MB - Last synced at: 9 months ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Code-Sample-Collection/VerilogHDL-Practical-insights

<轻松成为设计高手: VerilogHDL 实用精解> EDA 先锋工作室, 王诚, 吴继华 2012.6

Language: Verilog - Size: 269 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

hackerspace-ntnu/6502-macroprocessor

A large MOS 6502 processor replica, made for understanding and de-mystifying the inner workings of computers.

Language: JavaScript - Size: 2.95 MB - Last synced at: over 1 year ago - Pushed at: over 3 years ago - Stars: 5 - Forks: 0

ekb0412/100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Language: Verilog - Size: 12 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 9 - Forks: 1

maxs-well/Ethernet-design-verilog

Gigabit Ethernet UDP communication driver

Language: Verilog - Size: 30.3 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 43 - Forks: 34

michg/riscv32_beluga

c compiler beluga with riscv32 backend

Language: C - Size: 2.81 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 9 - Forks: 0

atharvaagiwal2/HDLBits-solution

HDLBits is a collection of 180+ circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL)

Language: Verilog - Size: 193 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

maxs-well/BPSK_verilog

BPSK verilog implemention

Language: Verilog - Size: 63.5 KB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 7 - Forks: 2

maxs-well/ad7606-driver-verilog

AD7606 driver verilog

Language: Verilog - Size: 3.88 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 23 - Forks: 8

AhmedAbdelaal2001/Advanced-Encryption-Standard

A full hardware implementation of the AES using Verilog, supporting SPI communication between all modules.

Language: Verilog - Size: 22.5 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

JayKaku/HDL-Bits-Solutions

HDL Bits solution

Language: Verilog - Size: 50.8 KB - Last synced at: about 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

vishalcseiitg/CS-577-C-BASED-VLSI-DESIGN

Course taken by Dr Chandan Karfa of Dept. of CSE, IIT Guwahati.

Language: C++ - Size: 71.2 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0