Vadman97/PicoSim

Xilinx Picoblaze Assembly Simulator and Debugger

Language: Python - Size: 54.7 KB - Last synced at: 7 months ago - Pushed at: over 8 years ago - Stars: 5 - Forks: 4

shrujan0274/HDLBits-submissions

Solutions for 100+ questions in HDLBits using verilog

Language: Verilog - Size: 37.1 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

mshr-h/fibonacci_verilog

fibonacci number calculator written in Verilog-HDL

Language: Verilog - Size: 41 KB - Last synced at: 5 months ago - Pushed at: over 8 years ago - Stars: 4 - Forks: 0

Ritvik2103/vending-machine-design

Vending Machine Design using Verilog HDL built and tested in Vivado Design Suite

Language: Verilog - Size: 161 KB - Last synced at: 11 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

Eyantra698Sumanto/Spice-to-Verilog-Converter

Spice to Verilog Converter

Language: Python - Size: 23.4 KB - Last synced at: 7 months ago - Pushed at: over 2 years ago - Stars: 12 - Forks: 1

kyori19/verilog-otp

VerilogHDL implementation of One-Time Password Algorithm (HOTP)

Language: SystemVerilog - Size: 6.84 KB - Last synced at: 4 months ago - Pushed at: about 3 years ago - Stars: 3 - Forks: 1

nk12U/2-Stage-Pipeline-4bit-CPU

2 Stage Pipeline 4bit CPU

Language: Verilog - Size: 12 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 1 - Forks: 0

Imtjl/digital-design-fundamentals

Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University

Language: Tcl - Size: 3.14 MB - Last synced at: 5 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

addisonElliott/LogiFindFPGATest

This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

Language: Verilog - Size: 1.7 MB - Last synced at: 8 months ago - Pushed at: about 6 years ago - Stars: 7 - Forks: 3

pragadheeshadhi/VLSI-design

comprehensive collection of HDL-based designs and implementations, including logic gates, adders, multipliers, decoders, flip-flops, counters, PRBS generators, memory modules, IIR/FIR filters, and interfacing circuits. This repository showcases modular, efficient, and scalable digital design solutions for various applications

Language: Verilog - Size: 5.86 KB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

Hiram8A/S_Box_LEDs

Implementación hardware de una S-Box (Substitution Box) del algoritmo AES (Advanced Encryption Standard) utilizando FPGA. El proyecto incluye el módulo de cifrado/descifrado y su testbench.

Language: Verilog - Size: 9.78 MB - Last synced at: 12 months ago - Pushed at: 12 months ago - Stars: 0 - Forks: 0

yasnakateb/SdramController

🛠 A SDRAM controller in Verilog HDL

Language: Verilog - Size: 47.9 KB - Last synced at: 8 months ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

mongrelgem/Verilog-Adders

Implementing Different Adder Structures in Verilog

Language: Verilog - Size: 77.1 KB - Last synced at: 10 months ago - Pushed at: about 6 years ago - Stars: 60 - Forks: 16

AnjanaSenanayake/verilog-model-for-8bit-processor

An implementation of a processor with basic components coded in verilog

Language: Verilog - Size: 6.84 KB - Last synced at: 5 months ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 2

AnjanaSenanayake/verilog-model-for-4bit-alu

4 bit ALU in verilog

Language: Verilog - Size: 1.95 KB - Last synced at: about 1 month ago - Pushed at: about 8 years ago - Stars: 1 - Forks: 1

HIMANK729/Verilog-Projects

Implementing Verilog projects. Memory Controller,FIFO,Hamming code(error detection & correction)

Language: Verilog - Size: 108 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

ANSHVIVEKMALHOTRA/Miniproject-HEATWATCH

HEATWATCH(Temperature monitoring system)-[Digital and System Designs]

Language: Verilog - Size: 39.1 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 2

gcardi/HDL

Informational materials for a course on logic networks, HDLs and programmable logic arrays (FPGAs).

Size: 34.4 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

splAcharya/DigitalOscilloscope_Zynq7000Soc

A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.

Size: 71.2 MB - Last synced at: about 1 year ago - Pushed at: over 5 years ago - Stars: 18 - Forks: 4

samiyaalizaidi/FIFO-In-Verilog

Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL

Language: Verilog - Size: 9.77 KB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

samiyaalizaidi/Direct-Digital-Synthesizer

Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL

Language: Verilog - Size: 220 KB - Last synced at: 9 months ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

socks2309/neural-network-fpga

This project is part of the B.Tech degree in Electronics and Telecommunication Engineering at KIIT University.

Language: Verilog - Size: 21.5 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 1

PavlosTzitzos/HDLs-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

Language: SystemVerilog - Size: 20.1 MB - Last synced at: 3 months ago - Pushed at: almost 2 years ago - Stars: 1 - Forks: 0

peplxx/keyboard-driver-vhdl

Driver for handling matrix keyboard 4x4 on FPGA Board

Language: Verilog - Size: 2.93 KB - Last synced at: 6 months ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

yasnakateb/AES

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

Language: Verilog - Size: 32.2 KB - Last synced at: 8 months ago - Pushed at: over 3 years ago - Stars: 3 - Forks: 0

williaml33moore/bathtub Fork of everactive/bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Language: SystemVerilog - Size: 7.61 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 2 - Forks: 0

Unicamp-Odhin/SPI-Master

SPI Master module written in Verilog HDL

Language: Makefile - Size: 5.86 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 1 - Forks: 0

deba0272/NIELIT_VLSI_1_WEEK_TRAINING_PROGRAM

Size: 1.57 MB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

Nidhinchandran47/DV200

A go-to repository for exploring, learning, and mastering RTL design and verification.

Language: Verilog - Size: 895 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 0

RDSik/digital-design-lab-manual

Мое решение задач из книги Цифровой синтез: практический курс

Language: Verilog - Size: 63.5 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

HarinandanAM/FPGA

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.

Language: VHDL - Size: 82 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

yuri-panchul/tt08-adder-with-flow-control Fork of TinyTapeout/tt08-verilog-template

Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.

Language: SystemVerilog - Size: 43.9 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 3 - Forks: 1

YosefRezazadeh/Altera-DE2-Projects

My FPGA practices on Altera-DE2-115 board with Verilog

Language: Verilog - Size: 11.7 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

hwlabnitc/hwlabnitc.github.io

Main website of the HW Lab guide by NITC

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KarimZakzouk/AES

Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.

Language: Verilog - Size: 24.4 KB - Last synced at: about 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

milton-pagan/basic-risc-microprocessor

Implementation of a basic RISC microprocessor based on ARM architecture. Course project for ICOM4215.

Language: Verilog - Size: 419 KB - Last synced at: 7 months ago - Pushed at: over 5 years ago - Stars: 1 - Forks: 1

Teddy-van-Jerry/ARM_Lite

A lite version of ARM CPU that extends ARM LEGv8

Language: Verilog - Size: 2.83 MB - Last synced at: 8 months ago - Pushed at: almost 4 years ago - Stars: 9 - Forks: 1

ahmd-kamel/UART-Verilog-Design

Design and Verification of UART IP that allows serial communication between two systems.

Language: Verilog - Size: 391 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

camilaqPereira/oficina-verilog-siecomp

Neste repositório estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

Language: Verilog - Size: 950 KB - Last synced at: 8 months ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

vSasakiv/RV32I_Processor

Risc-V 32i processor written in the Verilog HDL

Language: Verilog - Size: 6.61 MB - Last synced at: about 1 year ago - Pushed at: almost 3 years ago - Stars: 6 - Forks: 0

gyanesh10/Synchronous-FIFO

Synchronous FIFO

Size: 39.1 KB - Last synced at: about 1 year ago - Pushed at: about 1 year ago - Stars: 0 - Forks: 0

b1f6c1c4/Deep-DarkFantasy

Global Dark Mode for ALL apps on ANY platforms.

Language: Verilog - Size: 3.95 MB - Last synced at: 2 months ago - Pushed at: about 2 years ago - Stars: 17 - Forks: 0

Haaris-RTL/8-bit-CPU

RTL code of an 8-bit CPU designed in Verilog.

Language: Verilog - Size: 97.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

Swarup1747/Cache-Compression-Implementation-on-FPGA-using-Verilog-HDL

Cache Compression using Verilog HDL

Size: 82 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

ujjwal-2001/HDL-Bits-Solutions

This repo contains HDL-bits solutions. I tried to provide multiple solutions for the same problem, with comments.

Language: Verilog - Size: 48.8 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

amirah-sri/all_verilog

I am trying to develop my skills through daily practice and consistency.

Language: Verilog - Size: 735 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

JOKleinGe1/min_sys_riscv

Minimal system project with riscv core picorv32 : asm startup + linker script + c example + verilog system + testbench + Makefile

Language: Verilog - Size: 186 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 1

praveenarla/Linear-Convolution

Implementing Convolution of two digital functions each is a sequence of 8 samples,each represented in 2’s compliment form using 8 bits to produce the outputs(15 samples in total) using appropriate number of bits in 2’s compliment form using Verilog. Discrete Convolution is commonly used in signal processing and image processing.

Language: Verilog - Size: 134 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

ucerd/Summer-School-2023_2

Summer School on Full Stack Open-Source Ecosystem for Processor Based Chip Design

Size: 59.3 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

spider-tronix/VLSI 📦

RISC V core implementation using Verilog.

Language: Verilog - Size: 1.53 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 22 - Forks: 4

PRAMOTHs-Repository/digital-alarm-clock

RTL design of digital alarm clock

Language: Verilog - Size: 219 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

sdasgup3/parallel-processor-design

Super scalar Processor design

Language: Verilog - Size: 137 KB - Last synced at: 7 months ago - Pushed at: about 11 years ago - Stars: 21 - Forks: 3

arghyadeep-m/hdlbits-solution

Solutions to selected problems on https://hdlbits.01xz.net/

Language: Verilog - Size: 15.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

jfoshea/Viterbi-Decoder-in-Verilog

An efficient implementation of the Viterbi decoding algorithm in Verilog

Language: Verilog - Size: 7.57 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 41 - Forks: 20

MaxwellJay256/FPGALab_2024 📦

HITSZ 2024 数字电子技术实验 FPGA Verilog 代码仓库

Language: Verilog - Size: 18.6 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Sanskar777/Dynamic-branch-predictor-in-pipelined-processors

Language: Verilog - Size: 253 KB - Last synced at: 9 months ago - Pushed at: almost 6 years ago - Stars: 6 - Forks: 1

utkarshad21/FSM-Sequence-Detector-using-Verilog

FSM: Sequence Detector using Verilog HDL

Language: Verilog - Size: 2.93 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

mohasnik/Network-On-Chip

RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.

Language: SystemVerilog - Size: 28.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

YajanaRao/Verilog

Verilog Programs

Language: Verilog - Size: 133 KB - Last synced at: about 1 month ago - Pushed at: over 4 years ago - Stars: 2 - Forks: 0

daringpatil3134/SPI_Serial_Peripheral_Interface_Verilog_Modules

Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

Language: Verilog - Size: 29.3 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 2

tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

Language: Verilog - Size: 56.6 KB - Last synced at: 8 months ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

Electronic-Simulations/RTL_Simulation

Contains simuations under Digital Electronics domain. HDL, VHDL based simulation results of various digital circuit blocks.

Language: Verilog - Size: 137 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

naresh0902/Washing_Machine_Controller

A Control System for Washing Machine in Verilog HDL and DE10 Lite Board

Language: Verilog - Size: 4.42 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

thedatabusdotio/fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Language: Verilog - Size: 21.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 103 - Forks: 23

yigitbektasgursoy/SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

Language: Verilog - Size: 781 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

unfortunatelygeek/alu_simulator

8-Bit ALU Simulator in Verilog, implemented on a NEXYS A7 FPGA

Language: Tcl - Size: 854 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

yigitbektasgursoy/Motion_Estimation_Hardware_Verilog

Motion Estimation implementation by using Verilog HDL

Language: Verilog - Size: 2.85 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 5 - Forks: 0

yunkai1841/HC-SR04-FPGA

Measure the distance using HC-SR04 ultrasonic sensor on FPGA.

Language: Verilog - Size: 6.84 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 2 - Forks: 0

krishnakumardangi/pipe-MIPS32

It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.

Language: Verilog - Size: 74.2 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

cnily03-hive/single-cycle-cpu

Single-Cycle CPU for Homework of Computer System Design in CUMT

Language: Verilog - Size: 900 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 6 - Forks: 0

mongrelgem/cMIPS

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Language: Verilog - Size: 4.09 MB - Last synced at: 10 months ago - Pushed at: about 6 years ago - Stars: 5 - Forks: 0

Nidhinchandran47/my_rtl_code

Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

Language: Verilog - Size: 1.67 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 10 - Forks: 1

viraj-dhanushka/Verilog-based-CPU

A 32-bit CPU which includes an ALU, a Register File, Control Unit, Data and Instruction memory

Language: Verilog - Size: 876 KB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

Rudra-Joshi-002/Verilog_Codes

This Repository shows the implementation and results of various codes that I write in Verilog HDL

Language: Verilog - Size: 19.2 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

Erfangholiz/My-VHDL

A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.

Language: Verilog - Size: 383 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

abphilip-vit/CollegeP1

College - Digital Lock

Language: Verilog - Size: 4.53 MB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

abphilip-vit/College2

College - Lab Tasks of Digital Circuit Design

Language: HTML - Size: 29.1 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

RamtinS/circut-design

The repository contains code from a voluntary assignment in the course IDATT2104 Network Programming.

Language: Verilog - Size: 62.5 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

manuemmanuel/Gates-Verilog-HDL

This repository contains a collection of basic digital logic gates implemented in Verilog HDL (Hardware Description Language).

Language: Verilog - Size: 7.81 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

1rsh/EC39004

This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur

Language: Verilog - Size: 4.23 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

powerplayer9/Voice-Based-Motor-Control

A verilog HDL based project to control a servomotor with voice commands from an android phone.

Language: Verilog - Size: 547 KB - Last synced at: over 1 year ago - Pushed at: about 6 years ago - Stars: 11 - Forks: 2

icglue/icglue

A Tcl-Library for scripted HDL generation

Language: Tcl - Size: 1.6 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 12 - Forks: 2

garimaa-goyal/HDLBits-Solutions

Solutions to the practice questions of Verilog given on HDLBits

Language: Verilog - Size: 52.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

tommathew01/Verilog_S4_KTU

All Verilog programs as prescribed by KTU 2019 syllabus for CSE S4 Digital Lab

Language: Verilog - Size: 3.91 KB - Last synced at: over 1 year ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1

princeranjan03/ImageEncryption_I-CHIP

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

Language: Verilog - Size: 7.3 MB - Last synced at: 8 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

PrasunDatta/Traffic-Light-Controller-Using-VerilogHDL

This work is the final project of the sessional course - "EEE 304: Digital Electronics Laboratory". In this work, we have implemented a 4 way traffic controller system.

Size: 322 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

PrasunDatta/4-bit-PC-Using-VerilogHDL

This project is mainly focused on the course - "EEE 415 Microprocessors and Embedded Systems". Here we have designed a 4 bit PC using VerilogHDL.

Language: Verilog - Size: 4.81 MB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

jg-fossh/Goldschmidt_Integer_Divider_Parallel

A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.

Language: Verilog - Size: 82.4 MB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 9 - Forks: 2

guntas-13/Verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

Language: Verilog - Size: 50.7 MB - Last synced at: 5 months ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 1

Rohit04121998/Traffic-Controller

This project consists of a simple verilog code for traffic controller

Size: 55.7 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 1

Rohit04121998/Day-Of-The-Week

This project consists of a verilog code for calculating the day of a week from any given date between the years 1700 to 2300

Size: 6.84 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

nakamotoo/3S_Hardware_Design

Homework of Verilog HDL

Language: Verilog - Size: 13.7 KB - Last synced at: over 1 year ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

Robin329/VerilogThings

Some exercises on verilog.

Language: Verilog - Size: 76.2 KB - Last synced at: over 1 year ago - Pushed at: almost 2 years ago - Stars: 0 - Forks: 0

rakshitbajaj16/hdlBits_solutions

HDLBits — Verilog PracticeHDLBits is a collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL).

Size: 10.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

shyamal-anadkat/WISC-SP13

CS 552 term project : functional design of a microprocessor called the WISC-SP13

Language: Assembly - Size: 148 MB - Last synced at: 3 months ago - Pushed at: over 8 years ago - Stars: 4 - Forks: 6

rv2442/16BitScientificCalculator

16 Bit Scientific Calculator Using Xilinx ISE 14.7 on Xilinx ISE, EDA Playground and Simple 4 bit calculator on Spartan 6 Board

Language: C - Size: 961 KB - Last synced at: over 1 year ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 2

Abhirecket/Restoring-Division

Restoring division for unsigned integer.

Language: Verilog - Size: 182 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 1 - Forks: 0

Afkeen2004/S4-Hardware-Laboratory

S4 Hardware Laboratory

Language: Verilog - Size: 53.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

MiddleJo/4-Digit-Counter

4-Digit Counter with Verilog.

Language: Verilog - Size: 11.7 KB - Last synced at: over 1 year ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

tdurkut/BIL331

Bilgisayar Organizasyonu Verilog Projeleri

Language: Verilog - Size: 2.08 MB - Last synced at: over 1 year ago - Pushed at: almost 8 years ago - Stars: 0 - Forks: 0