djzenma/RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

Language: Verilog - Size: 3.19 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 11 - Forks: 2

wesamnabeel99/FPGA_LAB

This repository is intended for students who study Electrical Engineering at University of Baghdad, as well as anyone else who wants to learn about FPGA programming.

Language: VHDL - Size: 1.37 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

AlPrime2k1/Sequential-Logic-Circuits

Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

Language: Verilog - Size: 22.5 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Inmoresentum/CSE460GroupProject

Contains CSE460 Group Project Verilog code.

Language: Verilog - Size: 24.4 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

maxs-well/LMS-sound-filtering-by-Verilog

LMS sound filtering by Verilog

Language: Verilog - Size: 10.3 MB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 14 - Forks: 5

Venkaraddi7/Elevator_Controller

To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.

Language: Verilog - Size: 1.58 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

prithvi-narayan-bhat/Custom_RISC_Implementation

An attempt at making a customised RISC processor with five pipelined stages and supporting all RISC-V instruction set

Language: SystemVerilog - Size: 72.7 MB - Last synced at: almost 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

Simon-Hoffmann/CPU

Custom 32Bit CPU implementaion

Language: VHDL - Size: 11.8 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

gonultasbu/PicoTETRIS

Tetris game written for PicoBlaze softprocessor that runs on a Spartan 3E FPGA, VGA interface written with Verilog.

Language: Verilog - Size: 1.83 MB - Last synced at: about 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 1

KevinHexin/FPGA-Bicubic-interpolation

use Verilog HDL implemente bicubic interpolation in FPGA

Language: Coq - Size: 2.07 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 9 - Forks: 3

AnuragSChatterjee/Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA

A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform Machine Learning models i.e. MLP Neural Networks on an FPGA using C, C++, Hardware Description Languages (HDL), High Level Synthesis (HLS) and Verilog.

Language: Verilog - Size: 7.25 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

sivananthampalaniappan/verilog_code

This repository is to learn verilog code for basic digital circuits

Language: Verilog - Size: 3.01 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

jg-fossh/IIR_FILTER

IIR Parallel Filter

Language: Python - Size: 2.89 MB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 1

IzyaSoft/EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

Language: Verilog - Size: 315 KB - Last synced at: 8 months ago - Pushed at: over 8 years ago - Stars: 6 - Forks: 0

NARDEEPsinghSHEKHAWAT/VERILOG-VLSI-CODES

Some codes I have implemented during my 10 day Training under VLSI DOMAIN

Size: 1000 Bytes - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

shuai132/DMA_AXIS_LTC2324_16

LTC2324-16 driver for Xilinx AXI-DMA

Language: VHDL - Size: 12.5 MB - Last synced at: 7 months ago - Pushed at: almost 6 years ago - Stars: 3 - Forks: 0

nitindinnu/verilogg

This repository contains verilog code of MUX, DEMUX, Adder, Subtractor, Encoder, Decoder, FlipFlops, Registers and counters

Language: Verilog - Size: 8.97 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

nitindinnu/systemverilog_nitindinnu

Learnings of IEEE System Verilog 1800-2012 standard.

Language: SystemVerilog - Size: 10.3 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

mircea-pavel-anton/VHDL-Decryption 📦

A small decryption module, written in Verilog, as a university assignment.

Language: Verilog - Size: 557 KB - Last synced at: about 1 month ago - Pushed at: almost 5 years ago - Stars: 3 - Forks: 0

FaithGriffin/CSARCH1_HDLProject2

Verilog structural model HDL program

Language: Verilog - Size: 119 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

Language: Verilog - Size: 391 KB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

oriod-malo/My-Custom-CPU-ISA-Assembly

A small CPU / ISA and a testbench that displays its instructions' equivalent in assembly&machine language.

Language: Verilog - Size: 150 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 1 - Forks: 0

teekamkhandelwal/Uart_tx_main

Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate through digital pin 0, digital pin 1.

Language: Verilog - Size: 17.6 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject3

Verilog structural model HDL program

Language: Verilog - Size: 109 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

ankangd/4bitPC

Verilog-HDL implementation of a simple 4-bit PC.

Language: SystemVerilog - Size: 695 KB - Last synced at: about 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

KarlJoad/ece497

ECE 497 - Special Project Research

Language: TeX - Size: 49 MB - Last synced at: over 1 year ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 1

b-garbacz/Neokeon128

Implementation of the neokeon block cipher

Language: Verilog - Size: 15.6 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

FaithGriffin/CSARCH1_HDLProject1

Verilog behavioral model HDL program

Language: Verilog - Size: 59.6 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

josipnigojevic/VerilogMineDetectingANN

Neural Network implemented in Verilog used for distinguishing if the wave that bounced back into the sonar bounced off a mine or a rock.

Language: C - Size: 11.3 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 0

Alenkruth/Coursera-HDL-for-FPGAs

Solutions to the Assignments

Language: VHDL - Size: 207 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 4 - Forks: 3

0marAmr/Single_Cycle_RISC-V_processor

Language: Verilog - Size: 563 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

0marAmr/Testbench-Generator

Language: Python - Size: 7.81 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

praveenVnktsh/Hardware-Accelerated-Motion-Estimation-using-FSBM-and-FPGA

FPGA Implementation of Full Search Block matching using an asynchronous handshake based FSM.

Language: VHDL - Size: 27.6 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 3 - Forks: 0

melissa-aguiar/TCC

FPGA embedded multicore processing of an iterative deconvolution method based on sparse data representation aimed at online reconstruction of energy in particle accelerators

Size: 7.43 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 1 - Forks: 0

BrianHGinc/BHG_I2C_init_RS232_debugger

A Verilog I2C initializer with integrated RS232 debugger.

Language: Verilog - Size: 31.3 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 5 - Forks: 0

josephkb87/VerilogBasics

Basics of Verilog implementation

Language: SystemVerilog - Size: 19.5 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

aklsh/getting-started-with-verilog

Verilog modules for beginners

Language: Verilog - Size: 44.9 KB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 18 - Forks: 9

neelkshah/MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Language: Verilog - Size: 138 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 64 - Forks: 13

armixz/32bit-ALU

32 bits ALU include 16 commands to run/Verilog Code (.v) + Digital Circuit (.circ)

Language: Verilog - Size: 134 KB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 3 - Forks: 0

aklsh/Hephaestus

8-Bit Processor

Language: Verilog - Size: 926 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 4 - Forks: 1

mateuspinto/FPGA_Verilog_Ballot_Box-TP2-ISL-UFV

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

Language: Verilog - Size: 10.1 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 1

mihir8181/VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Language: Verilog - Size: 3.45 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 21 - Forks: 3

tomtor/HDL-deflate

FPGA implementation of deflate (de)compress RFC 1950/1951

Language: Verilog - Size: 476 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 34 - Forks: 1

JAYRAM711/AHB2APB-PROTOCOL-BRIDGE

The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB

Size: 1.05 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 1

vishalcseiitg/cs577-c-based-vlsi-design-project

Language: C - Size: 4.64 MB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ahmedishraq/CSE460-Lab

CSE460 - VLSI Design

Language: HTML - Size: 5.81 MB - Last synced at: 7 months ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

Jed-Z/computer-organization-lab

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

Language: Verilog - Size: 13.8 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 45 - Forks: 22

maazm007/ALU-8-Bit-Adder

This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits

Language: C - Size: 918 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

parmAshu/spi-io-expander

THIS REPOSITORY CONTAINS DESIGN FILES FOR SPI TO 32 DIGITAL IO EXPANSION MODULE

Language: Verilog - Size: 62.5 KB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 0

nainshree-raj/VLSI-domain

Interfacing of FPGA & HPS on DE1-SoC.

Size: 1.08 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 1 - Forks: 0

MuballighHossain/Very-Large-Scale-Integration-BRAC-University

Size: 19.2 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 0

tharunchitipolu/Multi-operations-toolbox-with-baugh-wooley-multiplier

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier

Language: Verilog - Size: 52.7 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 7 - Forks: 1

MuballighHossain/Moore_Machine_VLSI

Language: Verilog - Size: 6.84 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 1

MuballighHossain/VLSI_FSM_Verilog_Simulation

Language: Verilog - Size: 2.96 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 2 - Forks: 1

tharunchitipolu/SHA-256-Verilog-HDL

SHA-2 (Secure Hash Algorithm 2), of which SHA-256 is a part, is one of the most popular hashing algorithms out there.

Language: Verilog - Size: 12.7 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

MatejGomboc/Verilog-I2S-Transciever

I2S transciever implemented in Verilog HDL

Language: Verilog - Size: 77.1 KB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 12 - Forks: 7

lightcode/8bit-computer

Simple 8-bit computer build in Verilog

Language: Verilog - Size: 76.2 KB - Last synced at: over 2 years ago - Pushed at: about 8 years ago - Stars: 31 - Forks: 4

ashishrana160796/verilog-starter-tutorials 📦

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

Language: Verilog - Size: 25.4 KB - Last synced at: over 2 years ago - Pushed at: almost 5 years ago - Stars: 34 - Forks: 17

harshbhosale01/HDLBits

In this repository, I will be adding my solutions to HDLBits practice problems

Language: Verilog - Size: 4.88 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 2 - Forks: 0

yh08037/Verilog-HDL

[2019.1] 논리회로 이론 및 설계 Verilog 문법 정리

Language: Verilog - Size: 3.91 MB - Last synced at: over 2 years ago - Pushed at: almost 6 years ago - Stars: 2 - Forks: 0

MADHAVAN001/simple-mips-processor-design Fork of BhavyaLight/ACA3001

Developing a MIPS-like microprocessor with cache

Language: C - Size: 5.32 MB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 0

osamaadam/pipeTemp 📦

pipeTemp is an application that monitors the temperature reported by an adc sensor.

Language: Verilog - Size: 766 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 0 - Forks: 0

AUCOHL/Classic-Playground 📦

A playground based on the classic version of the Cloud V IDE

Language: JavaScript - Size: 3.96 MB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 3 - Forks: 1

osamaadam/cpu-syouf-shamaa 📦

Simple 8-bit processor

Language: Verilog - Size: 335 KB - Last synced at: over 2 years ago - Pushed at: over 4 years ago - Stars: 0 - Forks: 0

mcdobr/asc-mips 📦

A five-staged pipelined MIPS description

Language: Verilog - Size: 596 KB - Last synced at: over 2 years ago - Pushed at: over 8 years ago - Stars: 0 - Forks: 0

jeffsxguo/codh-labs 📦

Source of USTC CODH Experiment(Advanced Class).

Language: Verilog - Size: 30.3 KB - Last synced at: 4 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

jeffsxguo/digital_electronics 📦

Source of USTC Digital Electromics Course ( Advanced Class).

Language: Verilog - Size: 17.6 KB - Last synced at: 4 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

sts08015/HDLBits_solution

My own HDLBits solution :)

Language: Verilog - Size: 77.1 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0

yasnakateb/Blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

Language: Verilog - Size: 42 KB - Last synced at: 8 months ago - Pushed at: over 5 years ago - Stars: 0 - Forks: 0

mohanadtalat91/Verilog-HDL

A Verilog HDL code

Language: Verilog - Size: 16.6 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

mhshabani79/MIPS-multi-cycle

MIPS multi cycle Verilog Implementation

Language: SystemVerilog - Size: 1.56 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

mhshabani79/MIPS-single-cycle

MIPS Single cycle Verilog Implementation

Language: SystemVerilog - Size: 1.06 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

aptx1231/BUAA_CO

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

Language: Verilog - Size: 25.1 MB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 72 - Forks: 18

gojimmypi/ulx3s-examples

Collection of various ulx3s examples

Language: Python - Size: 16.1 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 10 - Forks: 8

Kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.

Language: Verilog - Size: 78.1 KB - Last synced at: 19 days ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

AJAbanto/RISCV-pipelined

A pipelined version of my previous single-cycle implementation of the RISCV ISA

Language: C - Size: 41.7 MB - Last synced at: 12 months ago - Pushed at: about 4 years ago - Stars: 0 - Forks: 0

aniketsingh03/CacheMemory

This project is an implementation of cache memory with load and store instructions in Verilog.

Language: C - Size: 795 KB - Last synced at: 6 months ago - Pushed at: about 8 years ago - Stars: 2 - Forks: 1

lkmidas/Simple-door-lock-using-Verilog-HDL

A simulation of a 3-digit password lock on FPGA using Verilog HDL.

Language: Verilog - Size: 7.16 MB - Last synced at: over 2 years ago - Pushed at: about 5 years ago - Stars: 1 - Forks: 2

Kanishk-K-U/AHB2APB-Bridge-Controller

Designed AHB to APB Bridge Controller using Verilog and simulated it on ModelSIM

Language: Verilog - Size: 14.9 MB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

ECE320/riscv-tester

Tests your ECE 320 Single Cycle RISC-V Processor: Up to PD5

Language: Python - Size: 101 KB - Last synced at: over 2 years ago - Pushed at: almost 3 years ago - Stars: 3 - Forks: 0

melzareix/mips-pipeline

Mips Pipeline Processor

Language: Verilog - Size: 36.1 KB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 9 - Forks: 2

AbhilashDatta/RISC-Processor

This is a single cycle processor, which processes each instruction in single clock cycle, working on Instruction Set Architecture (ISA) specified in the documentation.

Language: Verilog - Size: 1.97 MB - Last synced at: over 2 years ago - Pushed at: almost 4 years ago - Stars: 1 - Forks: 0

wgranados/Starflux

CSCB58 Computer Organization Project on which runs on which runs on an Altera DE1-115 FPGA board

Language: Verilog - Size: 114 KB - Last synced at: about 1 year ago - Pushed at: over 8 years ago - Stars: 2 - Forks: 1

chance189/I2C_Master

Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable

Language: Verilog - Size: 89.8 KB - Last synced at: over 2 years ago - Pushed at: over 5 years ago - Stars: 3 - Forks: 3

akifislam/Simulation-on-ModelSim-with-Verilog-HDL

This repository contains codes of Verilog which is a Hardware Definition Language. These code can be easily compiled and simulate with a software called ModelSim.

Language: Verilog - Size: 5.86 KB - Last synced at: over 1 year ago - Pushed at: almost 4 years ago - Stars: 0 - Forks: 2

Jayanth-sharma/FIFO-design

Designed 32-bit data Width Sync FIFO and Synchronizer.

Language: Verilog - Size: 137 KB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

semahawk/icarium

Trying to implement a soft core SoC

Language: Verilog - Size: 559 KB - Last synced at: over 2 years ago - Pushed at: over 6 years ago - Stars: 4 - Forks: 0

AI-with-Tarun/AV-Workshops

Source-Code and Valuable Resources used in AV-Workshops

Language: Jupyter Notebook - Size: 1.4 MB - Last synced at: 6 months ago - Pushed at: almost 3 years ago - Stars: 0 - Forks: 0

birdybro/Nand2Tetris_MiSTer

Nand2Tetris for MiSTer (as a learning experience for me).

Language: Assembly - Size: 3.15 MB - Last synced at: about 1 month ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 1

imjp2020/UVM_FIFO_TB

This testbench is based on SV and UVM Class based to verify Verilog HDL Design

Language: SystemVerilog - Size: 22.5 KB - Last synced at: over 2 years ago - Pushed at: over 2 years ago - Stars: 0 - Forks: 0

ty-fel/Crane-Game

Crane Game using Custom Pipelined Processor

Language: VHDL - Size: 90.9 MB - Last synced at: 6 months ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

Alireza-Zwolf/MIPS-PROCESSOR

An Implementation of MIPS processor with single/multi-cycle architecture using SystemVerilog language.

Language: SystemVerilog - Size: 1.76 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

kaushanr/System-Bus-Design

Design of a system bus architecture - Team Project @ ENTC UoM

Language: Verilog - Size: 10.1 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 1 - Forks: 2

chacal1231/Autoquarium

Es un producto que busca la automatización de su pecera, el objetivo principal es brindar el control total esta, con eso usted y su familia podrán salir y no preocuparse por dejar a sus peces. Autoquarium disponde de las siguientes funcionalidades. Medición de pH, nitrito, temperatura, Co2. Dispensador automático de comida programable por tiempo y tipo de comida. Iluminación artificial para simular luz diurna y nocturna. Sistema de emergencia en caso de fallas en la red eléctrica. Filtrado y limpieza del agua utilizada en la pecera. Acceso remoto a panel de estado, donde podrá controlar y ver el estado en tiempo real de sus peces. Notificaciones de estado vital de la pecera vía SMS y correo. Despliegue de la información en pantalla LCD.

Language: JavaScript - Size: 18.7 MB - Last synced at: over 1 year ago - Pushed at: over 8 years ago - Stars: 1 - Forks: 1

pendkeomkar/SPI

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

Size: 8.96 MB - Last synced at: over 2 years ago - Pushed at: about 7 years ago - Stars: 8 - Forks: 2

yangtiming/Digital-circuit-and-system-experiment

Digital circuit and system experiment

Language: Verilog - Size: 39.4 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 0

SorianoJuan/MIPS

32-bit MIPS processor implementation

Language: Verilog - Size: 4.24 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 1 - Forks: 1

Soham-coder/ROCC_based_neurosynapse

ROCC accelerator ISA based neuroSynapse

Language: SystemVerilog - Size: 1.67 MB - Last synced at: over 2 years ago - Pushed at: about 4 years ago - Stars: 1 - Forks: 1

kelvinleong0529/RISC-MIPS

FPGA design and implementation of multi-cycle 32-bits pipelined MIPS processor

Language: C - Size: 2.4 MB - Last synced at: over 2 years ago - Pushed at: about 3 years ago - Stars: 0 - Forks: 0

Dev-Goel/CSL2070-DD-Labs

Digital Design based labs, under Prof. Nitin Bhatia in course CSL2070.

Language: Verilog - Size: 4.43 MB - Last synced at: over 2 years ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0