GitHub topics: verilog-hdl

Repositories

JN513/Baby-Risco-5

Multi-cycle RISC-V processor with RV32E implementation

Language: Tcl - Size: 1.2 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

RV-Arun22/RTL-practice-projects

Verilog modules

Language: Verilog - Size: 42 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

Sibakumarpanda/UP_Counter_4bit_Verification_with_UVM

UP_Counter_4bit_Verification_with_UVM

Language: SystemVerilog - Size: 175 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

pranav-m-r/CS-F215-Digital-Design

My code files for the Digital Design (CS F215) course at BITS Pilani.

Language: Verilog - Size: 87.9 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

niloufarnb/pipelined-arm-verilog

Modular pipelined ARM CPU in Verilog — includes Fetch, Decode, Execute, Memory, and WriteBack stages with testbenches.

Language: Verilog - Size: 87.9 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

RDSik/schoolRISCV Fork of zhelnio/schoolRISCV

CPU microarchitecture, step by step

Language: Makefile - Size: 15.3 MB - Last synced at: about 1 month ago - Pushed at: 5 months ago - Stars: 1 - Forks: 0

SKpro-glitch/Parallel_Multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

Language: SystemVerilog - Size: 17.6 KB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 2 - Forks: 0

Choaib-ELMADI/getting-started-with-verilog

Getting started with Verilog: Hardware Description Language for digital design.

Language: Verilog - Size: 9.87 MB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 7 - Forks: 0

JASLemos/RV32I

A 32 bit RISC-V RV32I CPU described in Verilog HDL.

Language: VHDL - Size: 14.1 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

HANANDA1/FPGA-Based-Smart-Car-Security-System

FPGA-Based Smart Car Security System is a robust solution for protecting high-end vehicles like Porsche. It uses Verilog and SystemVerilog to detect unauthorized access and disable the fuel pump, ensuring your car remains secure. 🛠️🚗

Language: Verilog - Size: 9.27 MB - Last synced at: 5 months ago - Pushed at: 5 months ago - Stars: 0 - Forks: 0

sakethakella/ALU-Design

ALU Built with proper Datapath and Control path (FSM) to give appropriate results

Language: Verilog - Size: 13.7 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

bharathkumar419/verilog

Size: 1000 Bytes - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

dpretet/async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Language: Verilog - Size: 1.01 MB - Last synced at: 6 months ago - Pushed at: over 1 year ago - Stars: 349 - Forks: 83

Shuregg/riscv-simple-cpu

Creating a risc-v processor

Language: SystemVerilog - Size: 4.58 MB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 3 - Forks: 0

Pa1mantri/VSD_Hardware_Design

Pre and Post Synthesis Simulation of a Design VSDMemSOC

Language: Verilog - Size: 6.63 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 2 - Forks: 1

VadanShah/aes-apb-ctr

An AES-128 encryption module in CTR mode with APB interface, implemented in Verilog for FPGA-based secure data communication systems.

Language: Verilog - Size: 10.7 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

SNRomon27/Combinational-Logic-Design-Using-Verilog-HDL

Basic combinational logic design using Verilog hardware description language (HDL). A step-by-step basic combinational logic design using built-in primitives. Used Vivado 2018.3 as a text editor and simulator.

Language: Verilog - Size: 136 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

Subbu-kata/SSIT

This project implements a smart, contactless water dispensing system using FPGA technology. Designed for hygiene-critical environments, the system uses infrared (IR) proximity sensors to detect hand presence and activates a centrifigual pump for flow of water accordingly—eliminating the need for physical contact.

Language: Verilog - Size: 15.6 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

WilliamZhang20/Digital-Hardware-Blocks

Fundamental Digital Logic Concepts in Verilog

Language: Verilog - Size: 23.4 KB - Last synced at: 5 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

pvgupta24/Von-Neumann-Architecture-CPU

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

Language: Verilog - Size: 204 KB - Last synced at: 17 days ago - Pushed at: about 8 years ago - Stars: 6 - Forks: 1

jge162/verilog_compiler

Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.

Language: Verilog - Size: 520 KB - Last synced at: about 1 month ago - Pushed at: about 1 year ago - Stars: 15 - Forks: 0

web-cipher-007/Software-Engineering-Verilog-Labworks

Digital Design Labworks implemented in Verilog HDL for Software Engineering IOE, TU.

Language: SystemVerilog - Size: 0 Bytes - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

bojackchen/digital-flow

This is a tutorial on standard digital design flow

Language: Tcl - Size: 710 KB - Last synced at: 4 months ago - Pushed at: over 4 years ago - Stars: 78 - Forks: 30

littlepeace2005/RISC-V-Single-Cycle-Processor

A simple implementation of an RISC-V processor using Verilog.

Language: Verilog - Size: 685 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

yasnakateb/NoCRouter

🎞️ NoC router in Verilog with FIFO

Language: Verilog - Size: 269 KB - Last synced at: 4 months ago - Pushed at: about 3 years ago - Stars: 12 - Forks: 2

AUCOHL/Fault

A complete open-source design-for-testing (DFT) Solution

Language: Swift - Size: 4.3 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 153 - Forks: 32

Vihaan004/mips-multicycle-processor

A modular MIPS multicycle processor implementation focused on simulation, analysis, and educational exploration of processor design.

Language: Tcl - Size: 1.71 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

yasnakateb/Threshold

🖼✏️ My first baby steps into the world of image processing

Language: Verilog - Size: 1.85 MB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

shinowtf/FGPA-RFID-Door-Access-Gate-control-with-DE2-115

This is my University Digital System Assignment which using Verilog HDLCode to code DE2-115 board for RFID access card door control

Language: Verilog - Size: 1.39 MB - Last synced at: 3 months ago - Pushed at: 11 months ago - Stars: 0 - Forks: 0

amitops2103/Verilog-Assignment

Verilog practice sessions by Mr. Sujit Panda

Language: Verilog - Size: 904 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 1

Unicamp-Odhin/SPI-Slave

SPI Slave module written in SystemVerilog HDL

Language: Tcl - Size: 38.1 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 1 - Forks: 0

mcleber/Verilog_Testbench_Essentials

Creating testbenches in Verilog is an essential practice to verify the functionality of your modules and ensure your design behaves as expected.

Language: Verilog - Size: 66.4 KB - Last synced at: 6 months ago - Pushed at: 6 months ago - Stars: 0 - Forks: 0

mcleber/Verilog_7-Segment_Display_with_DIP_Switches

This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.

Language: Verilog - Size: 816 KB - Last synced at: 5 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

mcleber/Verilog_Traffic_Light_Controller

First steps with the Sipeed Tang Primer 20k FPGA.

Language: Verilog - Size: 1.75 MB - Last synced at: 6 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

ashkan-khd/conways-game-of-life-verilog

An easy approach for Conway's Game Of Life with Verilog HDL

Language: Verilog - Size: 6.84 KB - Last synced at: 4 months ago - Pushed at: about 2 years ago - Stars: 4 - Forks: 0

JN513/Pequeno-Risco-5

Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.

Language: Verilog - Size: 340 KB - Last synced at: 3 months ago - Pushed at: over 1 year ago - Stars: 7 - Forks: 0

hyeokls/HDL-Bits

베릴로그 문제 은행 풀이

Language: Verilog - Size: 199 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

samiyaalizaidi/Equalizer

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

Language: Verilog - Size: 536 KB - Last synced at: 5 months ago - Pushed at: 11 months ago - Stars: 7 - Forks: 1

sayandeepmaity/luminator

Microphone Array-Based Direction of Arrival of Gunshot Detection .Gun violence remains a critical concern. Identifying the precise location of a gunshot—or getting as close as humanly possible—is crucial for saving lives and ensuring public safety.

Language: Jupyter Notebook - Size: 163 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

AritraAmbudhDutta/IITK-Mini-MIPS

A MIPS processor implementation with integer and floating-point operations, supporting R-type, I-type, branch, and jump instructions.

Language: Verilog - Size: 103 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

mramyasri777/Vending-Machine

The Vending Machine Controller is a digital IP that manages item dispensing and change handling based on currency input. It supports flexible configuration, high-speed operation at 100 MHz, and efficient stock management through an APB interface.

Language: Verilog - Size: 4.88 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

Krishnasa1/vending_machine

This project implements a Verilog-based Vending Machine Controller with support for APB configuration, item dispensing, and currency validation. It features FSM control, clock domain synchronization, and is fully synthesizable for FPGA applications.

Size: 0 Bytes - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

SOWJANYA-MADANA/Vending-Machine

A Verilog-based RTL design of a configurable vending machine controller with APB configuration, asynchronous input handling, and real-time item dispensing.

Size: 0 Bytes - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

TahirZia-1/Digital-Clock-Verilog

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

Language: Tcl - Size: 283 KB - Last synced at: about 1 month ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

JN513/verilog-buses-implementations

Popular bus implementations in Verilog HDL

Language: Verilog - Size: 9.77 KB - Last synced at: 5 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

Mozes-Y/HDLBits_Solutions

My HDLBits solutions.

Language: Verilog - Size: 57.6 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 6 - Forks: 1

SKpro-glitch/Resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

Size: 270 KB - Last synced at: 21 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 1

s-okai/sv-style-guide

A SystemVerilog style guide.

Size: 20.5 KB - Last synced at: 3 months ago - Pushed at: over 9 years ago - Stars: 2 - Forks: 0

dau-dev/vivado-docker

Minimal Dockerized Vivado

Language: Shell - Size: 5.86 KB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

HarmandeepArneja/ReflexRush

Reaction Time Testing Game

Language: Verilog - Size: 0 Bytes - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

inhald/asip_stepper_motor_control

8-bit RISC ASIP for Stepper Motor Controller with both full and half step capabilities. Implemented in Verilog HDL.

Language: Verilog - Size: 10 MB - Last synced at: 18 days ago - Pushed at: 7 months ago - Stars: 0 - Forks: 0

pboechat/ice40up5k_tests

Multiple test designs for the iCE40UP5K-B-EVN board.

Language: Verilog - Size: 35.3 MB - Last synced at: 7 months ago - Pushed at: 7 months ago - Stars: 1 - Forks: 0

Lukas0025/yosys-cgploss

use genetic algoritms for optimalize circuits

Language: C++ - Size: 426 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

SKpro-glitch/RISCV-Processor-ASIC

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

Language: Verilog - Size: 138 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

defparam/higan-verilog

This is a higan/Verilator co-simulation example/framework

Language: C++ - Size: 1.36 MB - Last synced at: 7 months ago - Pushed at: over 7 years ago - Stars: 50 - Forks: 7

TheSUPERCD/8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Language: Verilog - Size: 173 KB - Last synced at: 8 months ago - Pushed at: almost 3 years ago - Stars: 54 - Forks: 15

Wissance/QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Language: Verilog - Size: 127 KB - Last synced at: 8 months ago - Pushed at: almost 8 years ago - Stars: 22 - Forks: 7

ihdavjar/EEL2020_Project_EVM

This repo contains the EEL2020 course project, which was instructed to be made in hindi.

Language: HTML - Size: 2.15 MB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 1 - Forks: 0

wdevore/Verilog-6809

Handcrafted MC6809 in Verilog

Size: 1000 Bytes - Last synced at: 8 months ago - Pushed at: about 5 years ago - Stars: 0 - Forks: 0

wdevore/Verilog-Projects

Collection of verilog modules and projects

Language: Verilog - Size: 55.3 MB - Last synced at: 8 months ago - Pushed at: over 3 years ago - Stars: 0 - Forks: 0

luk3Sky/Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

Language: Verilog - Size: 880 KB - Last synced at: 8 months ago - Pushed at: almost 7 years ago - Stars: 8 - Forks: 1

continuum5531/RISC-V

This project features a 32-bit accumulator-based processor designed following the Von Neumann architecture, optimized for efficient computation. It implements a 16-opcode instruction set with multiple addressing modes, ensuring flexibility in instruction execution and data manipulation.

Language: Verilog - Size: 20.5 KB - Last synced at: 6 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

ridhimach12/VHDL

This repository contains various Verilog implementations of fundamental digital circuits.Each module is tested with a corresponding Testbench for simulation in EDA Playground

Language: Verilog - Size: 45.9 KB - Last synced at: 8 months ago - Pushed at: 8 months ago - Stars: 0 - Forks: 0

chili-chips-ba/openXC7-TetriSaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

Language: Verilog - Size: 25.1 MB - Last synced at: 8 months ago - Pushed at: 9 months ago - Stars: 24 - Forks: 1

TahirZia-1/UART

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

Language: SystemVerilog - Size: 231 KB - Last synced at: 4 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Safa-Taha/Nand2Tetris

Nand2Tetris using Verilog

Language: Verilog - Size: 133 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

Foynguyn/CE213_HDL

My homework in HDL class

Language: Verilog - Size: 29.3 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

ultraembedded/cores

Various HDL (Verilog) IP Cores

Language: Verilog - Size: 211 KB - Last synced at: 9 months ago - Pushed at: over 4 years ago - Stars: 745 - Forks: 218

tvlad1234/violet

Virtual I/O for FPGAs

Language: Verilog - Size: 58.6 KB - Last synced at: 8 months ago - Pushed at: 9 months ago - Stars: 2 - Forks: 0

calvinee/FPGA-Technology-Weekly

分享FPGA相关的新闻，好技术文章，博客和项目，帮助大家入门FPGA系统开发，和工作创业交流。Share FPGA-related news, quality technical articles, blogs, and projects to help everyone get started with FPGA system development and exchange ideas on work and entrepreneurship.

Size: 14.6 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

JN513/fpga_basics

Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog

Language: Verilog - Size: 59.6 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 1 - Forks: 0

1sand0s/SSP-Master-and-Slave-Verilog-Module

FSM based SPI/SSP Master and Slave Verilog Module

Language: Verilog - Size: 4.88 KB - Last synced at: 8 months ago - Pushed at: almost 6 years ago - Stars: 4 - Forks: 2

s-okai/hello-fpga

A series of lessons on writing HDL for FPGAs.

Size: 11.7 KB - Last synced at: 3 months ago - Pushed at: over 8 years ago - Stars: 2 - Forks: 0

mthszr/stopwatch

Projeto para a disciplina IF675 de Sistemas Digitais no CIn-UFPE, no qual consiste em desenvolver um cronômetro digital, utilizando Verilog com a base de Máquina de Estados Finitos.

Language: Verilog - Size: 14.6 KB - Last synced at: about 1 month ago - Pushed at: over 1 year ago - Stars: 0 - Forks: 0

cspang1/jcap

JAMMA Custom Arcade Project

Language: Propeller Spin - Size: 98 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 13 - Forks: 3

ultraembedded/core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Language: Verilog - Size: 171 KB - Last synced at: 9 months ago - Pushed at: over 3 years ago - Stars: 221 - Forks: 43

istiak8empire/Hands-on-Project-of-Verilog-HDL

Implementing Hands-on Project of Verilog-HDL

Language: Verilog - Size: 1.98 MB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

ubyhzargam/Verilog

These are Verilog (HDL) codes.

Language: Verilog - Size: 208 KB - Last synced at: 9 months ago - Pushed at: 9 months ago - Stars: 0 - Forks: 0

BrianHGinc/Verilog-Floating-Point-Clock-Divider

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

Language: Verilog - Size: 289 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 14 - Forks: 1

MohamedHussein27/SPI_Slave_With_Single_Port_Memory

This repository contains the implementation of an SPI (Serial Peripheral Interface) communication protocol with sigle port sync RAM. The project includes the design and code for an SPI Slave, a single-port asynchronous RAM, and an SPI Wrapper that connects the RAM and SPI Slave.

Language: Verilog - Size: 2.18 MB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 5 - Forks: 0

prabalraj18/Adder

This repository contains Verilog implementations and testbenches for various types of adders, ranging from basic to advanced designs. Each adder is verified using testbenches and follows a structured approach to digital circuit design.

Size: 4.88 KB - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0

MalakSadek/StaticTimingAnalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

Language: HTML - Size: 1.2 MB - Last synced at: 7 months ago - Pushed at: over 4 years ago - Stars: 6 - Forks: 3

sbaldzenka/TangNano4k_examples

Examples for Gowin Tang Nano 4k FPGA-board.

Language: C - Size: 1.13 MB - Last synced at: 9 months ago - Pushed at: over 3 years ago - Stars: 9 - Forks: 4

ishifr/fpga_prototyping_codes

FPGA prototyping by Verilog examples kitobini o'qish davomida yozilgan kodlar to'plami. Nexys4DDR(Artix-7) dev board'dan foydalanilgan. A collection of code written while reading the book FPGA prototyping by Verilog examples. Nexys4DDR(Artix-7) dev board is used

Language: Tcl - Size: 0 Bytes - Last synced at: 10 months ago - Pushed at: 10 months ago - Stars: 0 - Forks: 0